Improve write_verilog specify support
[yosys.git] / frontends / ast /
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-24 Sylvain MunautMake return value of $clog2 signed
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space...
2018-11-04 Clifford WolfMerge pull request #687 from trcwm/master
2018-11-04 Clifford WolfMerge pull request #688 from ZipCPU/rosenfell
2018-11-03 ZipCPUMake and dependent upon LSB only
2018-11-01 Clifford WolfDo not generate "reg assigned in a continuous assignmen...
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface...
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the...
2018-10-20 Ruben UndheimFixed memory leak
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect
2018-10-17 Clifford WolfMerge pull request #660 from tklam/parse-liberty-detect...
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
2018-10-17 Clifford WolfMerge pull request #658 from daveshah1/ecp5_bram
2018-10-17 Clifford WolfMerge pull request #641 from tklam/master
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-13 Ruben UndheimDocumentation improvements etc.
2018-10-12 Ruben UndheimFix build error with clang
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix
2018-10-02 Clifford WolfMerge pull request #646 from tomverbeure/issue594
2018-10-02 Tom VerbeureFix for issue 594.
2018-10-01 Dan GisselquistAdd read_verilog $changed support
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master
2018-09-30 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-30 Clifford WolfFix handling of $past 2nd argument in read_verilog
2018-09-24 Udi FinkelsteinFixed issue #630 by fixing a minor typo in the previous...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-09-17 Udi FinkelsteinFixed remaining cases where we check fo wire reg/wire...
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master
2018-08-27 Jim LawsonMerge branch 'master' into firrtl+modules+shiftfixes
2018-08-27 Jim LawsonMerge pull request #3 from YosysHQ/master
2018-08-23 Clifford WolfMerge pull request #610 from udif/udif_specify_round2
2018-08-23 Clifford WolfMerge pull request #614 from udif/pr_disable_dump_ptr
2018-08-23 Udi FinkelsteinAdded -no_dump_ptr flag for AST dump options in 'read_v...
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file...
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-07-21 Henner ZellerFix remaining log_file_error(); emit dependent file...
2018-07-20 Clifford WolfMerge pull request #586 from hzeller/more-sourcepos...
2018-07-20 Henner ZellerConvert more log_error() to log_file_error() where...
2018-07-20 Clifford WolfMerge pull request #585 from hzeller/use-file-warning...
2018-07-20 Henner ZellerUse log_file_warning(), log_file_error() functions.
2018-07-20 Clifford WolfMerge pull request #584 from hzeller/provide-source...
2018-07-19 Henner ZellerProvide source-location logging.
2018-07-04 Aman GoelMerge branch 'YosysHQ-master'
2018-07-04 Aman GoelMerging with official repo
2018-06-28 Clifford WolfFix handling of signed memories
2018-06-05 Udi FinkelsteinModified errors into warnings
2018-06-01 Clifford WolfAdd (* gclk *) attribute support
2018-05-04 Clifford WolfMerge pull request #537 from mithro/yosys-vpr
2018-05-03 Clifford WolfReplace -ignore_redef with -[no]overwrite
2018-03-11 Udi FinkelsteinThis PR should be the base for discussion, do not merge...
2018-02-23 Clifford WolfMerge branch 'forall'
2018-02-23 Clifford WolfAdd $allconst and $allseq cell types
2018-01-07 Clifford WolfAdd support for "yosys -E"
2018-01-05 Clifford WolfMerge pull request #479 from Fatsie/latch_without_data
2018-01-05 Clifford WolfBugfix in hierarchy handling of blackbox module ports
2017-12-09 Clifford WolfMerge branch 'master' into btor-ng
2017-12-02 Clifford WolfFix error handling for nested always/initial
2017-11-09 dh73Merge https://github.com/cliffordwolf/yosys
2017-10-10 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-10-10 Clifford WolfRemove some dead code
2017-10-10 Clifford WolfAllow $past, $stable, $rose, $fell in $global_clock...
2017-10-03 Clifford WolfMerge branch 'pr_ast_const_funcs' of https://github...
2017-09-30 Udi FinkelsteinTurned a few member functions into const, esp. dumpAst...
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check...
2017-09-29 Clifford WolfMerge pull request #425 from udif/udif_dollar_bits
2017-09-26 Udi Finkelstein$size() now works correctly for all cases!
2017-09-26 Udi Finkelstein$size() seems to work now with or without the optional...
2017-09-26 Udi Finkelsteinenable $bits() and $size() functions only when the...
2017-09-26 Udi FinkelsteinAdded $bits() for memories as well.
2017-09-26 Udi Finkelstein$size() now works with memories as well!
2017-09-26 Udi FinkelsteinAdd $size() function. At the moment it works only on...
2017-06-07 Clifford WolfFix generation of vlogtb output in yosys-smtbmc for...
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-23 Clifford WolfPreserve string parameters
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