2018-10-01 |
Aman Goel | Merge pull request #4 from YosysHQ/master |
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2018-09-17 |
Udi Finkelstein | Merge branch 'master' into pr_reg_wire_error |
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2018-09-14 |
Clifford Wolf | Merge pull request #625 from aman-goel/master |
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2018-08-27 |
Jim Lawson | Merge branch 'master' into firrtl+modules+shiftfixes |
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2018-08-27 |
Jim Lawson | Merge pull request #3 from YosysHQ/master |
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2018-08-27 |
Clifford Wolf | Add "make coverage" |
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2018-08-22 |
Jim Lawson | Merge pull request #1 from YosysHQ/master |
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2018-08-18 |
Aman Goel | Merge pull request #3 from YosysHQ/master |
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2018-08-15 |
Clifford Wolf | Merge pull request #573 from cr1901/msys-64 |
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2018-08-15 |
Clifford Wolf | Merge pull request #591 from hzeller/virtual-override |
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2018-07-21 |
Henner Zeller | Consistent use of 'override' for virtual methods in... |
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2016-10-22 |
Clifford Wolf | Added avail params to ilang format, check module params... |
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2016-10-14 |
Clifford Wolf | Added $global_clock verilog syntax support for creating... |
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2016-07-08 |
Clifford Wolf | Merge branch 'yosys-0.5-vtr' of https://github.com... |
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2016-04-23 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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2016-04-21 |
Clifford Wolf | Added "yosys -D" feature |
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2015-12-07 |
Clifford Wolf | Merge pull request #108 from cseed/master |
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2015-11-29 |
Clifford Wolf | Fixed oom bug in ilang parser |
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2015-11-27 |
Clifford Wolf | Fixed performance bug in ilang parser |
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2015-10-25 |
Clifford Wolf | Import more std:: stuff into Yosys namespace |
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2015-08-13 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2015-08-12 |
Clifford Wolf | Adjust makefiles to work with out-of-tree builds |
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2015-07-02 |
Clifford Wolf | Fixed trailing whitespaces |
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2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2015-01-08 |
Clifford Wolf | Merge pull request #46 from utzig/master |
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2015-01-08 |
Fabio Utzig | Enable bison to be customized |
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2015-01-01 |
Clifford Wolf | Fixed memory->start_offset handling |
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2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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2014-10-23 |
Clifford Wolf | Re-introduced Yosys::readsome() helper function |
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2014-10-14 |
Clifford Wolf | Merge branch 'win32' |
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2014-10-14 |
Clifford Wolf | Updated .gitignore file for ilang and verilog frontends |
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2014-10-14 |
William Speirs | Updated lexers & parsers to include prefixes |
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2014-10-11 |
Clifford Wolf | Fixed win32 troubles with f.readsome() |
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2014-09-27 |
Clifford Wolf | namespace Yosys |
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2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2014-08-23 |
Clifford Wolf | Changed frontend-api from FILE to std::istream |
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2014-08-14 |
Clifford Wolf | Added module->ports |
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2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
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2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module... |
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2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
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2014-07-28 |
Clifford Wolf | Added wire->upto flag for signals such as "wire [0... |
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2014-07-27 |
Clifford Wolf | Fixed ilang parser for new RTLIL API |
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2014-07-26 |
Clifford Wolf | Changed a lot of code to the new RTLIL::Wire constructors |
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2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
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2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
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2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
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2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
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2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
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2014-07-25 |
Clifford Wolf | Use only module->addCell() and module->remove() to... |
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2014-07-24 |
Clifford Wolf | Added "make PRETTY=1" |
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2014-07-23 |
Clifford Wolf | Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL... |
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2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
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2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::size()... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: using the accessor functions every... |
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2014-07-22 |
Clifford Wolf | SigSpec refactoring: renamed chunks and width to __chun... |
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2014-07-22 |
Clifford Wolf | Fixed ilang parsing of process attributes |
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2014-07-22 |
Clifford Wolf | Fixed make rules for ilang parser |
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2014-07-21 |
Clifford Wolf | Added "autoidx" statement to ilang file format |
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2014-04-20 |
Clifford Wolf | Fixed clang -Wdeprecated-register warnings |
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2014-04-20 |
Clifford Wolf | Replaced depricated %name-prefix= bison directive |
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2014-03-07 |
Clifford Wolf | Bugfix in ilang frontend autoidx recovery |
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2014-02-12 |
Clifford Wolf | Merge pull request #26 from ahmedirfan1983/btor |
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2014-02-11 |
Clifford Wolf | renamed ilang "scope error" to "ilang error" |
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2014-02-09 |
Clifford Wolf | Improved ilang parser error messages |
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2014-02-01 |
Clifford Wolf | Fixed comment/eol parsing in ilang frontend |
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2014-01-14 |
Ahmed Irfan | Merge branch 'master' of https://github.com/ahmedirfan1... |
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2014-01-03 |
Clifford Wolf | Added updating of RTLIL::autoidx to ilang frontend |
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2013-12-04 |
Clifford Wolf | Replaced signed_parameters API with CONST_FLAG_SIGNED |
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2013-11-24 |
Clifford Wolf | Added support for signed parameters in ilang |
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2013-11-24 |
Clifford Wolf | Remove auto_wire framework (smarter than the verilog... |
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2013-11-21 |
Clifford Wolf | Major improvements in mem2reg and added "init" sync... |
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2013-11-20 |
Clifford Wolf | Fixed ilang parser: memory width |
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2013-10-23 |
Clifford Wolf | Fixed parsing of value-less attributes in ilang |
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2013-05-23 |
Clifford Wolf | Fixed memory leak in ilang frontend |
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2013-03-01 |
Clifford Wolf | Added help messages to ilang and verilog frontends |
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2013-01-05 |
Clifford Wolf | added .gitignore files |
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2013-01-05 |
Clifford Wolf | initial import |
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