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read_ilang: detect overflow of integer literals.
[yosys.git] / frontends / ilang /
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream tree | commitdiff
2014-08-14 Clifford WolfAdded module->ports tree | commitdiff
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added... tree | commitdiff
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module... tree | commitdiff
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys... tree | commitdiff
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0... tree | commitdiff
2014-07-27 Clifford WolfFixed ilang parser for new RTLIL API tree | commitdiff
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors tree | commitdiff
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname) tree | commitdiff
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell... tree | commitdiff
2014-07-26 Clifford WolfManual fixes for new cell connections API tree | commitdiff
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API... tree | commitdiff
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_ tree | commitdiff
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to... tree | commitdiff
2014-07-24 Clifford WolfAdded "make PRETTY=1" tree | commitdiff
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL... tree | commitdiff
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... tree | commitdiff
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::size()... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every... tree | commitdiff
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun... tree | commitdiff
2014-07-22 Clifford WolfFixed ilang parsing of process attributes tree | commitdiff
2014-07-22 Clifford WolfFixed make rules for ilang parser tree | commitdiff
2014-07-21 Clifford WolfAdded "autoidx" statement to ilang file format tree | commitdiff
2014-04-20 Clifford WolfFixed clang -Wdeprecated-register warnings tree | commitdiff
2014-04-20 Clifford WolfReplaced depricated %name-prefix= bison directive tree | commitdiff
2014-03-07 Clifford WolfBugfix in ilang frontend autoidx recovery tree | commitdiff
2014-02-12 Clifford WolfMerge pull request #26 from ahmedirfan1983/btor tree | commitdiff
2014-02-11 Clifford Wolfrenamed ilang "scope error" to "ilang error" tree | commitdiff
2014-02-09 Clifford WolfImproved ilang parser error messages tree | commitdiff
2014-02-01 Clifford WolfFixed comment/eol parsing in ilang frontend tree | commitdiff
2014-01-14 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1... tree | commitdiff
2014-01-03 Clifford WolfAdded updating of RTLIL::autoidx to ilang frontend tree | commitdiff
2013-12-04 Clifford WolfReplaced signed_parameters API with CONST_FLAG_SIGNED tree | commitdiff
2013-11-24 Clifford WolfAdded support for signed parameters in ilang tree | commitdiff
2013-11-24 Clifford WolfRemove auto_wire framework (smarter than the verilog... tree | commitdiff
2013-11-21 Clifford WolfMajor improvements in mem2reg and added "init" sync... tree | commitdiff
2013-11-20 Clifford WolfFixed ilang parser: memory width tree | commitdiff
2013-10-23 Clifford WolfFixed parsing of value-less attributes in ilang tree | commitdiff
2013-05-23 Clifford WolfFixed memory leak in ilang frontend tree | commitdiff
2013-03-01 Clifford WolfAdded help messages to ilang and verilog frontends tree | commitdiff
2013-01-05 Clifford Wolfadded .gitignore files tree | commitdiff
2013-01-05 Clifford Wolfinitial import tree | commitdiff