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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
[yosys.git]
/
frontends
/
liberty
/
liberty.cc
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-02-11
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
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2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
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2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
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2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
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2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
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2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-12-01
Clifford Wolf
Merge pull request #676 from rafaeltp/master
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2018-11-12
Clifford Wolf
Merge pull request #695 from daveshah1/ecp5_bb
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2018-11-05
Clifford Wolf
Allow square brackets in liberty identifiers
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2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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2018-10-18
Clifford Wolf
Merge pull request #657 from mithro/xilinx-vpr
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2018-10-18
Clifford Wolf
Merge pull request #664 from tklam/ignore-verilog-protect
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2018-10-17
Clifford Wolf
Minor code cleanups in liberty front-end
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2018-10-17
Clifford Wolf
Merge pull request #660 from tklam/parse-liberty-detect...
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2018-10-13
argama
detect ff/latch before processing other nodes
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-08-15
Clifford Wolf
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2018-07-04
Aman Goel
Merge branch 'YosysHQ-master'
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2018-07-04
Aman Goel
Merging with official repo
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2018-06-15
Clifford Wolf
Bugfix in liberty parser (as suggested by aiju in ...
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2018-05-13
Clifford Wolf
Merge pull request #505 from thefallenidealist/FreeBSD_...
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2018-05-12
Sergiusz Bazanski
Also interpret '&' in liberty functions
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2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
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2018-05-03
Clifford Wolf
Replace -ignore_redef with -[no]overwrite
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2018-02-16
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2018-02-15
Clifford Wolf
Improve handling of "bus" pins in liberty front-end...
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2018-01-05
Clifford Wolf
Merge pull request #479 from Fatsie/latch_without_data
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2018-01-03
Staf Verhaegen
Some standard cell libraries include a latch with only...
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2016-09-23
Clifford Wolf
Added liberty parser support for types within cell...
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2016-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/brouhaha...
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2016-09-18
Clifford Wolf
Added support for bus interfaces to "read_liberty ...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-23
Clifford Wolf
Changed frontend-api from FILE to std::istream
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2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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2014-08-02
Clifford Wolf
More bugfixes related to new RTLIL::IdString
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-31
Clifford Wolf
Added module->design and cell->module, wire->module...
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-07-21
Clifford Wolf
Replaced depricated NEW_WIRE macro with module->addWire...
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2014-07-21
Clifford Wolf
Removed deprecated module->new_wire()
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2014-07-16
Clifford Wolf
Added "inout" ports support to read_liberty
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2014-07-16
Clifford Wolf
Set blackbox attribute in "read_liberty -lib"
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2014-07-16
Clifford Wolf
Fixed spelling of "direction" in read_liberty messages
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2014-05-29
Clifford Wolf
Merge pull request #36 from hansiglaser/master
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2014-05-28
Johann Glaser
new flags -ignore_miss_func and -ignore_miss_dir for...
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2014-02-15
Clifford Wolf
Added ff and latch support to read_liberty
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2014-02-15
Clifford Wolf
Bugfix in expression parser of read_liberty
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2014-02-15
Clifford Wolf
Added liberty frontend
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