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Add Verific fairness/liveness support
[yosys.git]
/
frontends
/
verific
/
verific.cc
2017-10-12
Clifford Wolf
Add Verific fairness/liveness support
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2017-10-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-10-10
Clifford Wolf
Start work on pre-processor for Verific SVA properties
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2017-10-05
Clifford Wolf
Improve handling of Verific errors
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2017-10-04
Clifford Wolf
Improve Verific error handling, check VHDL static asserts
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2017-10-04
Clifford Wolf
Fix nasty bug in Verific bindings
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2017-07-28
Clifford Wolf
Add merging of "past FFs" to verific importer
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2017-07-28
Clifford Wolf
Add minimal support for PSL in VHDL via Verific
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2017-07-28
Clifford Wolf
Improve Verific HDL language options
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2017-07-28
Clifford Wolf
Fix handling of non-user-declared Verific netbus
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2017-07-27
Clifford Wolf
Improve Verific SVA importer
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2017-07-27
Clifford Wolf
Add log_warning_noprefix() API, Use for Verific warning...
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2017-07-27
Clifford Wolf
Add "verific -import -n" and "verific -import -nosva"
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2017-07-27
Clifford Wolf
Improve Verific SVA import: negedge and $past
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2017-07-27
Clifford Wolf
Improve Verific SVA importer
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2017-07-26
Clifford Wolf
Improve Verific bindings (mostly related to SVA)
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2017-07-25
Clifford Wolf
Improve "help verific" message
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2017-07-25
Clifford Wolf
Add "verific -extnets"
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2017-07-25
Clifford Wolf
Improve "verific -all" handling
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2017-07-24
Clifford Wolf
Add "verific -import -d <dump_file"
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2017-07-24
Clifford Wolf
Add "verific -import -flatten" and "verific -import -v"
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2017-07-22
Clifford Wolf
Add "verific -import -k"
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2017-07-04
Clifford Wolf
Add Verific Release information to log
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2017-02-11
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-11
Clifford Wolf
Add support for verific mem initialization
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2017-02-11
Clifford Wolf
Fix another stupid bug in the same line
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2017-02-11
Clifford Wolf
Add verific support for initialized variables
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2017-02-11
Clifford Wolf
Improve handling of Verific warnings and error messages
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2017-02-11
Clifford Wolf
Fix extremely stupid typo
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2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
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2017-02-09
Clifford Wolf
Add "rand" and "rand const" verific support
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2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-08
Clifford Wolf
Add PSL parser mode to verific front-end
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2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
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2017-02-04
Clifford Wolf
Add assert/assume support to verific front-end
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2016-02-13
Clifford Wolf
Support for more Verific primitives (patch I got per...
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2016-02-03
Clifford Wolf
Bugfix in Verific front-end
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2016-02-02
Clifford Wolf
Added addBufGate module method
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-11-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-11-24
Clifford Wolf
Added PRIM_DLATCHRS support to verific front-end
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2015-11-16
Clifford Wolf
Fixed performance bug in Verific importer
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2015-11-12
Clifford Wolf
Changes for Verific 3.16_484_32_151112
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2015-10-25
Clifford Wolf
Import more std:: stuff into Yosys namespace
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2015-09-25
Clifford Wolf
Added read-enable to memory model
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2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-05-17
Clifford Wolf
Verific build fixes
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-11-09
Clifford Wolf
Added log_warning() API
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2014-10-17
William Speirs
Header changes so it will compile on VS
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2014-10-10
Clifford Wolf
Renamed SIZE() to GetSize() because of name collision...
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-06
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-09-06
Clifford Wolf
Merge pull request #38 from rubund/master
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2014-09-06
Ruben Undheim
Corrected spelling mistakes found by lintian
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2014-08-16
Clifford Wolf
Added module->uniquify()
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2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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2014-08-12
Clifford Wolf
Fixed building verific bindings
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2014-07-31
Clifford Wolf
Fixed build of verific bindings
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2014-07-31
Clifford Wolf
Added module->design and cell->module, wire->module...
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Fixed verific bindings for new RTLIL api
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2014-07-23
Clifford Wolf
Various fixes in Verific frontend for new RTLIL API
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2014-03-20
Clifford Wolf
Fixed mapping of Verific WIDE_DFFRS operator
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2014-03-20
Clifford Wolf
Fixed mapping of Verific FADD primitive with unconnecte...
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2014-03-17
Clifford Wolf
Progress in Verific bindings
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2014-03-17
Clifford Wolf
Progress in Verific bindings
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2014-03-17
Clifford Wolf
Progress in Verific bindings
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2014-03-16
Clifford Wolf
Added support for memories to verific bindings
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2014-03-16
Clifford Wolf
Use Verific Net::{IsGnd,IsPwr} API in Verific bindings
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2014-03-15
Clifford Wolf
Progress in Verific bindings
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2014-03-15
Clifford Wolf
Progress in Verific bindings
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2014-03-15
Clifford Wolf
Progress in Verific bindings
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2014-03-14
Clifford Wolf
Progress in Verific bindings
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2014-03-14
Clifford Wolf
Progress in Verific bindings
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2014-03-13
Clifford Wolf
Progress in Verific bindings
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2014-03-13
Clifford Wolf
Copy Verific vdbs files to Yosys "share" data directory
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2014-03-10
Clifford Wolf
Improved verific command (added support for some operators)
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2014-03-10
Clifford Wolf
Improvements in verific command
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2014-03-09
Clifford Wolf
Added "verific" command
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