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[yosys.git] / frontends / verilog / parser.y

2013-11-20	Clifford Wolf	Implemented part/bit select on memory read	blob \| commitdiff \| raw
2013-11-20	Clifford Wolf	Added init= attribute for fpga-style reset values	blob \| commitdiff \| raw \| diff to current
2013-11-19	Clifford Wolf	Fixed parsing of module arguments when one type is...	blob \| commitdiff \| raw \| diff to current
2013-11-13	Clifford Wolf	Fixed parsing of "parameter integer"	blob \| commitdiff \| raw \| diff to current
2013-11-07	Clifford Wolf	Various fixes for correct parameter support	blob \| commitdiff \| raw \| diff to current
2013-10-24	Clifford Wolf	Fixed handling of boolean attributes (frontends)	blob \| commitdiff \| raw \| diff to current
2013-10-24	Clifford Wolf	Fixed handling of boolean attributes (kernel)	blob \| commitdiff \| raw \| diff to current
2013-07-04	Clifford Wolf	Added defparam support to Verilog/AST frontend	blob \| commitdiff \| raw \| diff to current
2013-06-13	Clifford Wolf	More fixes for bugs found using xsthammer	blob \| commitdiff \| raw \| diff to current
2013-06-07	Clifford Wolf	Added SAT generator and simple sat_solve command	blob \| commitdiff \| raw \| diff to current
2013-05-16	Clifford Wolf	Merge branch 'bugfix'	blob \| commitdiff \| raw \| diff to current
2013-03-31	Clifford Wolf	Added AST_INITIAL (before verilog "initial" was mapped...	blob \| commitdiff \| raw \| diff to current
2013-03-23	Clifford Wolf	Tiny fixes to verilog parser	blob \| commitdiff \| raw \| diff to current
2013-02-26	Clifford Wolf	Added support for verilog genblock[index].member syntax	blob \| commitdiff \| raw \| diff to current
2013-01-16	Clifford Wolf	Added support for "always @(*)"	blob \| commitdiff \| raw \| diff to current
2013-01-05	Clifford Wolf	initial import	blob \| commitdiff \| raw \| diff to current

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