ecp5: fix rebase mistake
[yosys.git] / frontends / verilog / preproc.cc
2020-04-10 whitequarkMerge pull request #1603 from whitequark/ice40-ram_style
2020-04-08 Sahand KashaniMerge branch 'master' of github.com:YosysHQ/yosys into...
2020-04-07 Claire WolfMerge pull request #1814 from YosysHQ/mmicko/pyosys_mak...
2020-04-02 Eddie HungMerge pull request #1853 from YosysHQ/eddie/fix_dynslice
2020-04-02 Claire WolfMerge pull request #1842 from YosysHQ/mwk/fix-deminout-xz
2020-04-02 Eddie HungMerge pull request #1845 from YosysHQ/eddie/kernel_speedup
2020-04-02 Claire WolfMerge pull request #1770 from YosysHQ/claire/btor_symbols
2020-04-02 Claire WolfMerge pull request #1765 from YosysHQ/claire/btor_info
2020-04-01 Eddie HungMerge pull request #1828 from YosysHQ/eddie/celltypes_s...
2020-04-01 Eddie HungMerge pull request #1790 from YosysHQ/eddie/opt_expr_xor
2020-04-01 Eddie HungMerge pull request #1789 from YosysHQ/eddie/opt_expr_alu
2020-04-01 Claire WolfMerge pull request #1848 from YosysHQ/eddie/fix_dynslice
2020-03-31 Eddie HungMerge pull request #1761 from YosysHQ/eddie/opt_merge_s...
2020-03-30 Eddie HungMerge pull request #1783 from boqwxp/astcc_cleanup
2020-03-30 Eddie HungMerge pull request #1835 from boqwxp/cleanup_sat_expose
2020-03-30 Eddie HungMerge pull request #1832 from boqwxp/cleanup_passes_cmd...
2020-03-30 Eddie HungMerge pull request #1786 from boqwxp/hierarchycc_cleanup
2020-03-30 Eddie HungMerge pull request #1831 from boqwxp/cleanup_sat_eval
2020-03-30 Eddie HungMerge pull request #1833 from boqwxp/cleanup_sat_freduce
2020-03-30 N. EngelhardtMerge pull request #1811 from PeterCrozier/typedef_scope
2020-03-30 N. EngelhardtMerge pull request #1778 from rswarbrick/sv-defines
2020-03-27 Rupert SwarbrickAdd support for SystemVerilog-style `define to Verilog...
2020-02-01 Eddie HungMerge branch 'master' into eddie/submod_po
2020-01-29 Claire WolfMerge branch 'vector_fix' of https://github.com/Kmanfi...
2020-01-29 N. EngelhardtMerge pull request #1510 from pumbor/master
2020-01-29 Miodrag MilanovićMerge pull request #1559 from YosysHQ/efinix_test_fix
2020-01-28 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2020-01-28 Claire WolfMerge pull request #1567 from YosysHQ/eddie/sat_init_wa...
2020-01-28 N. EngelhardtMerge pull request #1573 from YosysHQ/eddie/xilinx_tristate
2020-01-28 Claire WolfMerge pull request #1553 from whitequark/manual-dffx
2020-01-27 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2020-01-03 N. EngelhardtMerge branch 'master' of https://github.com/YosysHQ...
2019-12-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 Eddie HungMerge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
2019-12-19 Eddie HungMerge pull request #1569 from YosysHQ/eddie/fix_1531
2019-12-19 Eddie HungMerge pull request #1571 from YosysHQ/eddie/fix_1570
2019-12-18 David ShahMerge pull request #1563 from YosysHQ/dave/async-prld
2019-12-18 Eddie HungMerge pull request #1572 from nakengelhardt/scratchpad_pass
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram
2019-12-16 Eddie HungMerge branch 'diego/memattr' of https://github.com...
2019-12-16 Eddie HungMerge pull request #1575 from rodrigomelo9/master
2019-12-16 Eddie HungMerge pull request #1577 from gromero/for-yosys
2019-12-13 Rodrigo Alejandro... Fixed some missing "verilog_" in documentation
2019-11-22 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-11-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-10 Clifford WolfMerge pull request #1470 from YosysHQ/clifford/subpassdoc
2019-11-07 Clifford WolfAdd check for valid macro names in macro definitions
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-07-04 Aman GoelMerge branch 'YosysHQ-master'
2018-07-04 Aman GoelMerging with official repo
2018-05-17 Clifford WolfMerge pull request #550 from jimparis/yosys-upstream
2018-05-17 Jim ParisSupport SystemVerilog `` extension for macros
2018-05-17 Jim ParisSkip spaces around macro arguments
2018-01-07 Clifford WolfAdd support for "yosys -E"
2017-11-28 Clifford WolfMerge pull request #462 from daveshah1/up5k
2017-11-24 Clifford WolfMerge pull request #446 from mithro/travis-rework
2017-11-18 Clifford WolfMerge pull request #455 from daveshah1/up5k
2017-11-18 Clifford WolfMerge pull request #452 from cr1901/master
2017-11-14 William D. JonesAccommodate Windows-style paths during include-file...
2017-09-26 Clifford WolfMerge branch 'vlogpp-inc-fixes'
2017-09-26 Clifford WolfMinor coding style fix
2017-09-26 Clifford WolfMerge branch 'master' of https://github.com/combinatory...
2017-09-21 combinatorylogicAdding support for string macros and macros with argume...
2017-04-26 Clifford WolfAdd support for `resetall compiler directive
2017-03-14 Clifford WolfFix verilog pre-processor for multi-level relative...
2016-11-28 Clifford WolfAdded support for macros as include file names
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-13 Clifford WolfSystemVerilog also has assume(), added implicit -D...
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-14 Clifford WolfFixed handling of "//" in filenames in verilog pre...
2015-01-02 Clifford WolfDefine YOSYS and SYNTHESIS in preproc
2014-10-23 Clifford WolfRe-introduced Yosys::readsome() helper function
2014-10-14 Clifford WolfMerge branch 'win32'
2014-10-14 Clifford WolfReplaced readsome() with read() and gcount()
2014-10-11 Clifford WolfFixed win32 troubles with f.readsome()
2014-10-10 Clifford WolfAdded format __attribute__ to stringf()
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream
2014-08-14 Clifford WolfFixed line numbers when using here-doc macros
2014-08-13 Clifford WolfAdded support for non-standard """ macro bodies
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-30 Clifford WolfFixed counting verilog line numbers for "// synopsys...
2014-07-29 Clifford WolfFixed Verilog pre-processor for files with no trailing...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none"
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-18 Clifford WolfFixed parsing of verilog macros at end of line
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2013-12-27 Clifford WolfFixed parsing of non-arg macro calls followed by "("
2013-12-27 Clifford WolfFixed parsing of macros with no arguments and expansion...
2013-12-18 Clifford WolfAdded elsif preproc support
2013-12-18 Clifford WolfAdded support for macro arguments
2013-11-22 Clifford WolfFixed O(n^2) performance bug in verilog preprocessor
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