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Cover __APPLE__ too for little to big endian
[yosys.git]
/
frontends
/
verilog
/
preproc.cc
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-07-04
Aman Goel
Merge branch 'YosysHQ-master'
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2018-07-04
Aman Goel
Merging with official repo
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2018-05-17
Clifford Wolf
Merge pull request #550 from jimparis/yosys-upstream
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2018-05-17
Jim Paris
Support SystemVerilog `` extension for macros
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2018-05-17
Jim Paris
Skip spaces around macro arguments
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2018-01-07
Clifford Wolf
Add support for "yosys -E"
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2017-11-28
Clifford Wolf
Merge pull request #462 from daveshah1/up5k
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2017-11-24
Clifford Wolf
Merge pull request #446 from mithro/travis-rework
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2017-11-18
Clifford Wolf
Merge pull request #455 from daveshah1/up5k
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2017-11-18
Clifford Wolf
Merge pull request #452 from cr1901/master
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2017-11-14
William D. Jones
Accommodate Windows-style paths during include-file...
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2017-09-26
Clifford Wolf
Merge branch 'vlogpp-inc-fixes'
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2017-09-26
Clifford Wolf
Minor coding style fix
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2017-09-26
Clifford Wolf
Merge branch 'master' of https://github.com/combinatory...
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2017-09-21
combinatorylogic
Adding support for string macros and macros with argume...
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2017-04-26
Clifford Wolf
Add support for `resetall compiler directive
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2017-03-14
Clifford Wolf
Fix verilog pre-processor for multi-level relative...
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2016-11-28
Clifford Wolf
Added support for macros as include file names
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2016-11-15
Clifford Wolf
Remember global declarations and defines accross read_v...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-10-13
Clifford Wolf
SystemVerilog also has assume(), added implicit -D...
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-14
Clifford Wolf
Fixed handling of "//" in filenames in verilog pre...
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2015-01-02
Clifford Wolf
Define YOSYS and SYNTHESIS in preproc
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2014-10-23
Clifford Wolf
Re-introduced Yosys::readsome() helper function
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2014-10-14
Clifford Wolf
Merge branch 'win32'
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2014-10-14
Clifford Wolf
Replaced readsome() with read() and gcount()
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2014-10-11
Clifford Wolf
Fixed win32 troubles with f.readsome()
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2014-10-10
Clifford Wolf
Added format __attribute__ to stringf()
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-23
Clifford Wolf
Changed frontend-api from FILE to std::istream
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2014-08-14
Clifford Wolf
Fixed line numbers when using here-doc macros
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2014-08-13
Clifford Wolf
Added support for non-standard """ macro bodies
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-30
Clifford Wolf
Fixed counting verilog line numbers for "// synopsys...
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2014-07-29
Clifford Wolf
Fixed Verilog pre-processor for files with no trailing...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-02-17
Clifford Wolf
Added Verilog support for "`default_nettype none"
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2014-01-20
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-18
Clifford Wolf
Fixed parsing of verilog macros at end of line
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2013-12-27
Clifford Wolf
Fixed parsing of non-arg macro calls followed by "("
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2013-12-27
Clifford Wolf
Fixed parsing of macros with no arguments and expansion...
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2013-12-18
Clifford Wolf
Added elsif preproc support
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2013-12-18
Clifford Wolf
Added support for macro arguments
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2013-11-22
Clifford Wolf
Fixed O(n^2) performance bug in verilog preprocessor
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2013-11-22
Clifford Wolf
Enable {* .. *} feature per default (removes dependency...
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2013-08-20
Clifford Wolf
Merge pull request #9 from hansiglaser/master
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2013-08-20
Johann Glaser
Added support for include directories with the new...
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2013-05-19
Clifford Wolf
Merge pull request #6 from hansiglaser/master
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2013-05-19
Johann Glaser
added option '-Dname[=definition]' to command 'read_ver...
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2013-01-05
Clifford Wolf
initial import
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