Make genvar a signed type
[yosys.git] / frontends / verilog / verilog_frontend.cc
2019-06-20 Clifford WolfMerge branch 'unpacked_arrays' of https://github.com...
2019-06-19 Clifford WolfMerge pull request #1109 from YosysHQ/clifford/fix1106
2019-06-19 Clifford WolfAdd "read_verilog -pwires" feature, closes #1106
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-08 Clifford WolfMerge pull request #991 from kristofferkoch/gcc9-warnings
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-04-30 Clifford WolfMerge pull request #972 from YosysHQ/clifford/fix968
2019-04-30 Clifford WolfMerge pull request #966 from YosysHQ/clifford/fix956
2019-04-30 Clifford WolfMerge branch 'master' into eddie/refactor_synth_xilinx
2019-04-30 Clifford WolfMerge pull request #973 from christian-krieg/feature...
2019-04-30 Clifford WolfInclude filename in "Executing Verilog-2005 frontend...
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-23 Clifford WolfAdd specify parser
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #916 from YosysHQ/map_cells_before_m...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-22 Clifford WolfMerge pull request #945 from YosysHQ/clifford/libwb
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Clifford WolfNew behavior for front-end handling of whiteboxes
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-21 Clifford WolfImprove read_verilog debug output capabilities
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-08 Clifford WolfAdd "read_verilog -noassert -noassume -assert-assumes"
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master
2018-09-30 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-28 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-24 Clifford WolfAdd "read_verilog -noassert -noassume -assert-assumes"
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master
2018-08-27 Jim LawsonMerge branch 'master' into firrtl+modules+shiftfixes
2018-08-27 Jim LawsonMerge pull request #3 from YosysHQ/master
2018-08-23 Clifford WolfMerge pull request #610 from udif/udif_specify_round2
2018-08-23 Clifford WolfMerge pull request #614 from udif/pr_disable_dump_ptr
2018-08-23 Udi FinkelsteinAdded -no_dump_ptr flag for AST dump options in 'read_v...
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-07-20 Clifford WolfMerge pull request #585 from hzeller/use-file-warning...
2018-07-20 Henner ZellerUse log_file_warning(), log_file_error() functions.
2018-05-04 Clifford WolfMerge pull request #537 from mithro/yosys-vpr
2018-05-03 Clifford WolfReplace -ignore_redef with -[no]overwrite
2017-12-24 Clifford WolfBugfix in verilog_defaults argument parser
2017-07-21 Clifford WolfAdd a paragraph about pre-defined macros to read_verilo...
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-17 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-15 Clifford WolfAdded "verilog_defines" command
2016-11-28 Clifford WolfBugfix in "read_verilog -D NAME=VAL" handling
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v...
2016-08-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-08-26 Clifford WolfAdded read_verilog -norestrict -assume-asserts
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-27 Clifford WolfAdded "read_verilog -dump_rtlil"
2016-07-23 Clifford WolfNo tristate warning message for "read_verilog -lib"
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-05-20 Clifford WolfMerge branch 'master' of https://github.com/Kmanfi...
2016-05-20 Clifford WolfSmall improvements in Verilog front-end docs
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-03-11 Clifford WolfMerge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
2016-03-10 Clifford WolfFixed typos in verilog_defaults help message
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-13 Clifford WolfSystemVerilog also has assume(), added implicit -D...
2015-09-23 Clifford WolfAdded read_verilog -nodpi
2015-08-14 Clifford WolfRe-created command-reference-manual.tex, copied some...
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-08-01 Clifford WolfMerge pull request #68 from zeldin/master
2015-08-01 Marcus ComstedtAdd -noautowire option to verilog frontend
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-19 Clifford WolfVerilog front-end: define `BLACKBOX in -lib mode
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-26 Clifford WolfAdded non-std verilog assume() statement
2015-02-14 Clifford WolfAdded "read_verilog -nomeminit" and "nomeminit" attribute
2014-10-16 Clifford WolfPrint "SystemVerilog" in "read_verilog -sv" log messages
2014-09-27 Clifford Wolfnamespace Yosys
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