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Bugfix in verilog_defaults argument parser
[yosys.git]
/
frontends
/
verilog
/
verilog_frontend.cc
2017-12-24
Clifford Wolf
Bugfix in verilog_defaults argument parser
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2017-07-21
Clifford Wolf
Add a paragraph about pre-defined macros to read_verilo...
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2016-12-23
Andrew Zonenberg
Merge pull request #1 from azonenberg-hk/master
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2016-12-17
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-12-15
Clifford Wolf
Added "verilog_defines" command
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2016-11-28
Clifford Wolf
Bugfix in "read_verilog -D NAME=VAL" handling
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2016-11-15
Clifford Wolf
Remember global declarations and defines accross read_v...
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2016-08-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-08-26
Clifford Wolf
Added read_verilog -norestrict -assume-asserts
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2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-27
Clifford Wolf
Added "read_verilog -dump_rtlil"
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2016-07-23
Clifford Wolf
No tristate warning message for "read_verilog -lib"
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-05-20
Clifford Wolf
Merge branch 'master' of https://github.com/Kmanfi...
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2016-05-20
Clifford Wolf
Small improvements in Verilog front-end docs
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2016-03-11
Clifford Wolf
Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
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2016-03-10
Clifford Wolf
Fixed typos in verilog_defaults help message
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-10-13
Clifford Wolf
SystemVerilog also has assume(), added implicit -D...
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2015-09-23
Clifford Wolf
Added read_verilog -nodpi
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2015-08-14
Clifford Wolf
Re-created command-reference-manual.tex, copied some...
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2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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2015-08-01
Clifford Wolf
Merge pull request #68 from zeldin/master
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2015-08-01
Marcus Comstedt
Add -noautowire option to verilog frontend
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-19
Clifford Wolf
Verilog front-end: define `BLACKBOX in -lib mode
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-26
Clifford Wolf
Added non-std verilog assume() statement
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2015-02-14
Clifford Wolf
Added "read_verilog -nomeminit" and "nomeminit" attribute
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2014-10-16
Clifford Wolf
Print "SystemVerilog" in "read_verilog -sv" log messages
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-23
Clifford Wolf
Removed compatbility.{h,cc}: Not using open_memstream...
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2014-08-23
Clifford Wolf
Changed frontend-api from FILE to std::istream
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2014-08-21
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-08-21
Clifford Wolf
Added support for global tasks and functions
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-06-12
Clifford Wolf
Added read_verilog -sv options, added support for bit...
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2014-06-04
Clifford Wolf
Improved error message for options after front-end...
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2014-03-13
Clifford Wolf
Merge branch 'master' of https://github.com/Siesh1oo...
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2014-03-13
Clifford Wolf
Merged OSX fixes from Siesh1oo with some modifications
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2014-02-17
Clifford Wolf
Added Verilog support for "`default_nettype none"
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2014-02-16
Clifford Wolf
Added a warning note about error reporting to read_veri...
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2014-02-13
Clifford Wolf
Implemented read_verilog -defer
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2014-02-05
Clifford Wolf
Added read_verilog -setattr
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2014-02-02
Clifford Wolf
Added support for blanks after -I and -D in read_verilog
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2014-01-28
Clifford Wolf
Added read_verilog -icells option
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2014-01-18
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-17
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
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2014-01-17
Ahmed Irfan
Merge pull request #4 from cliffordwolf/master
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2014-01-17
Clifford Wolf
Added verilog_defaults command
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2013-11-24
Clifford Wolf
Added verilog frontend -ignore_redef option
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2013-11-22
Clifford Wolf
Renamed "placeholder" to "blackbox"
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2013-11-22
Clifford Wolf
Enable {* .. *} feature per default (removes dependency...
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2013-08-20
Clifford Wolf
Merge pull request #9 from hansiglaser/master
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2013-08-20
Johann Glaser
Added support for include directories with the new...
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2013-08-19
Clifford Wolf
Improved ast dumping (ast/verilog frontend)
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2013-06-10
Clifford Wolf
Enabled AST/Verilog front-end optimizations per default
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2013-05-19
Clifford Wolf
Merge pull request #6 from hansiglaser/master
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2013-05-19
Johann Glaser
added option '-Dname[=definition]' to command 'read_ver...
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2013-05-16
Clifford Wolf
Merge branch 'bugfix'
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2013-03-28
Clifford Wolf
Implemented proper handling of stub placeholder modules
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2013-03-24
Clifford Wolf
Added mem2reg option to verilog frontend
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2013-03-01
Clifford Wolf
Added help messages to ilang and verilog frontends
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2013-02-27
Clifford Wolf
Moved stand-alone libs to libs/ directory and added...
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2013-01-05
Clifford Wolf
initial import
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