Bugfix in verilog_defaults argument parser
[yosys.git] / frontends / verilog / verilog_frontend.cc
2017-12-24 Clifford WolfBugfix in verilog_defaults argument parser
2017-07-21 Clifford WolfAdd a paragraph about pre-defined macros to read_verilo...
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-17 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-15 Clifford WolfAdded "verilog_defines" command
2016-11-28 Clifford WolfBugfix in "read_verilog -D NAME=VAL" handling
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v...
2016-08-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-08-26 Clifford WolfAdded read_verilog -norestrict -assume-asserts
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-27 Clifford WolfAdded "read_verilog -dump_rtlil"
2016-07-23 Clifford WolfNo tristate warning message for "read_verilog -lib"
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-05-20 Clifford WolfMerge branch 'master' of https://github.com/Kmanfi...
2016-05-20 Clifford WolfSmall improvements in Verilog front-end docs
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-03-11 Clifford WolfMerge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
2016-03-10 Clifford WolfFixed typos in verilog_defaults help message
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-13 Clifford WolfSystemVerilog also has assume(), added implicit -D...
2015-09-23 Clifford WolfAdded read_verilog -nodpi
2015-08-14 Clifford WolfRe-created command-reference-manual.tex, copied some...
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-08-01 Clifford WolfMerge pull request #68 from zeldin/master
2015-08-01 Marcus ComstedtAdd -noautowire option to verilog frontend
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-19 Clifford WolfVerilog front-end: define `BLACKBOX in -lib mode
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-26 Clifford WolfAdded non-std verilog assume() statement
2015-02-14 Clifford WolfAdded "read_verilog -nomeminit" and "nomeminit" attribute
2014-10-16 Clifford WolfPrint "SystemVerilog" in "read_verilog -sv" log messages
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-23 Clifford WolfRemoved compatbility.{h,cc}: Not using open_memstream...
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream
2014-08-21 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-08-21 Clifford WolfAdded support for global tasks and functions
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-06-12 Clifford WolfAdded read_verilog -sv options, added support for bit...
2014-06-04 Clifford WolfImproved error message for options after front-end...
2014-03-13 Clifford WolfMerge branch 'master' of https://github.com/Siesh1oo...
2014-03-13 Clifford WolfMerged OSX fixes from Siesh1oo with some modifications
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none"
2014-02-16 Clifford WolfAdded a warning note about error reporting to read_veri...
2014-02-13 Clifford WolfImplemented read_verilog -defer
2014-02-05 Clifford WolfAdded read_verilog -setattr
2014-02-02 Clifford WolfAdded support for blanks after -I and -D in read_verilog
2014-01-28 Clifford WolfAdded read_verilog -icells option
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-17 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-17 Ahmed IrfanMerge pull request #4 from cliffordwolf/master
2014-01-17 Clifford WolfAdded verilog_defaults command
2013-11-24 Clifford WolfAdded verilog frontend -ignore_redef option
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox"
2013-11-22 Clifford WolfEnable {* .. *} feature per default (removes dependency...
2013-08-20 Clifford WolfMerge pull request #9 from hansiglaser/master
2013-08-20 Johann GlaserAdded support for include directories with the new...
2013-08-19 Clifford WolfImproved ast dumping (ast/verilog frontend)
2013-06-10 Clifford WolfEnabled AST/Verilog front-end optimizations per default
2013-05-19 Clifford WolfMerge pull request #6 from hansiglaser/master
2013-05-19 Johann Glaseradded option '-Dname[=definition]' to command 'read_ver...
2013-05-16 Clifford WolfMerge branch 'bugfix'
2013-03-28 Clifford WolfImplemented proper handling of stub placeholder modules
2013-03-24 Clifford WolfAdded mem2reg option to verilog frontend
2013-03-01 Clifford WolfAdded help messages to ilang and verilog frontends
2013-02-27 Clifford WolfMoved stand-alone libs to libs/ directory and added...
2013-01-05 Clifford Wolfinitial import