Fix broken abc9.v test due to inout being 1'bx
[yosys.git] / frontends / verilog / verilog_lexer.l
2019-06-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-20 Clifford WolfMerge branch 'unpacked_arrays' of https://github.com...
2019-06-18 Clifford WolfMerge pull request #1086 from udif/pr_elab_sys_tasks2
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-06-12 Eddie HungMerge branch 'xc7mux' of github.com:YosysHQ/yosys into...
2019-06-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-12 Eddie HungRevert "Add "-W' wire delay arg to abc9, use from synth...
2019-06-12 Eddie HungAdd "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-10 Udi FinkelsteinFixed brojen $error()/$info/$warning() on non-generate...
2019-06-08 Clifford WolfMerge pull request #1078 from YosysHQ/eddie/muxcover_costs
2019-06-07 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-06-07 Clifford WolfMerge pull request #1077 from YosysHQ/clifford/pr983
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-06-06 David ShahMerge pull request #1073 from whitequark/ecp5-diamond-iob
2019-06-05 Clifford WolfMerge pull request #999 from jakobwenzel/setundefInitFix
2019-05-31 Eddie HungMerge branch 'xaig' into xc7mux
2019-05-28 Clifford WolfMerge pull request #1049 from YosysHQ/clifford/fix1047
2019-05-28 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-28 Clifford WolfMerge pull request #1050 from YosysHQ/clifford/wandwor
2019-05-28 Clifford WolfMerge branch 'wandwor' of https://github.com/thasti...
2019-05-27 Stefan BiereigelMerge branch 'master' into wandwor
2019-05-27 Clifford WolfMerge pull request #1044 from mmicko/invalid_width_range
2019-05-27 Clifford WolfMerge pull request #1043 from mmicko/unsized_constant
2019-05-27 Miodrag MilanovicAdded support for unsized constants, fixes #1022
2019-05-23 Stefan Biereigelmake lexer/parser aware of wand/wor net types
2019-05-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-08 Clifford WolfMerge pull request #991 from kristofferkoch/gcc9-warnings
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfMerge pull request #871 from YosysHQ/verific_import
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-06 Clifford WolfMerge pull request #989 from YosysHQ/dave/abc_name_improve
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-04 Clifford WolfMerge pull request #988 from YosysHQ/clifford/fix987
2019-05-04 Clifford WolfAdd support for SVA "final" keyword
2019-05-04 Clifford WolfAdd approximate support for SV "var" keyword, fixes...
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Udi FinkelsteinInitial implementation of elaboration system tasks
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
2019-04-23 Clifford WolfUn-break default specify parser
2019-04-23 Clifford WolfAdd specify parser
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff
2019-03-11 Eddie HungMerge pull request #864 from YosysHQ/svalabelfix
2019-03-10 Clifford WolfFix handling of cases that look like sva labels, fixes...
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-09 Clifford WolfAlso add support for labels on sva module items, fixes...
2019-02-11 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire
2019-01-05 Clifford WolfBugfix in Verilog string handling
2018-12-18 Jim LawsonMerge remote-tracking branch 'upstream/master'
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect
2018-10-16 argamaignore protect endprotect
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master
2018-08-27 Jim LawsonMerge branch 'master' into firrtl+modules+shiftfixes
2018-08-27 Jim LawsonMerge pull request #3 from YosysHQ/master
2018-08-27 Clifford WolfAdd "make coverage"
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file...
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-05-04 Clifford WolfMerge pull request #537 from mithro/yosys-vpr
2018-05-03 Dan GisselquistSupport more character literals
2018-03-27 Udi FinkelsteinFirst draft of Verilog parser support for specify block...
2018-03-11 Udi FinkelsteinThis PR should be the base for discussion, do not merge...
2017-11-28 Clifford WolfMerge pull request #462 from daveshah1/up5k
2017-11-24 Clifford WolfMerge pull request #446 from mithro/travis-rework
2017-11-23 Clifford WolfMerge branch 'master' into btor-ng
2017-11-23 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-11-23 Clifford WolfAdd Verilog "automatic" keyword (ignored in synthesis)
2017-09-26 Clifford WolfMerge branch 'master' of https://github.com/combinatory...
2017-09-25 Clifford WolfFix ignoring of simulation timings so that invalid...
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-23 Clifford WolfAdd support for SystemVerilog unique, unique0, and...
2017-02-23 Clifford WolfAdded SystemVerilog support for ++ and --
2017-02-11 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Clifford WolfAdd checker support to verilog front-end
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-08 Clifford WolfAdd SV "rand" and "const rand" support
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