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Add support for SVA "final" keyword
[yosys.git]
/
frontends
/
verilog
/
verilog_lexer.l
2019-05-04
Clifford Wolf
Add support for SVA "final" keyword
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-12
Clifford Wolf
Merge pull request #866 from YosysHQ/clifford/idstuff
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2019-03-11
Eddie Hung
Merge pull request #864 from YosysHQ/svalabelfix
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2019-03-10
Clifford Wolf
Fix handling of cases that look like sva labels, fixes...
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-09
Clifford Wolf
Merge pull request #858 from YosysHQ/clifford/svalabels
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2019-03-09
Clifford Wolf
Also add support for labels on sva module items, fixes...
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2019-01-07
Clifford Wolf
Merge pull request #782 from whitequark/flowmap_dfs
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2019-01-06
Clifford Wolf
Merge pull request #780 from phire/rename_from_wire
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2019-01-05
Clifford Wolf
Bugfix in Verilog string handling
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2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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2018-10-18
Clifford Wolf
Merge pull request #657 from mithro/xilinx-vpr
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2018-10-18
Clifford Wolf
Merge pull request #664 from tklam/ignore-verilog-protect
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2018-10-16
argama
ignore protect endprotect
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2018-10-12
Ruben Undheim
Synthesis support for SystemVerilog interfaces
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2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
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2018-08-27
Jim Lawson
Merge branch 'master' into firrtl+modules+shiftfixes
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2018-08-27
Jim Lawson
Merge pull request #3 from YosysHQ/master
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2018-08-27
Clifford Wolf
Add "make coverage"
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-08-15
Clifford Wolf
Merge pull request #590 from hzeller/remaining-file...
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2018-08-15
Clifford Wolf
Merge pull request #576 from cr1901/no-resource
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2018-08-15
Clifford Wolf
Merge pull request #592 from japm48/master
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
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2018-05-03
Dan Gisselquist
Support more character literals
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2018-03-27
Udi Finkelstein
First draft of Verilog parser support for specify block...
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2018-03-11
Udi Finkelstein
This PR should be the base for discussion, do not merge...
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2017-11-28
Clifford Wolf
Merge pull request #462 from daveshah1/up5k
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2017-11-24
Clifford Wolf
Merge pull request #446 from mithro/travis-rework
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2017-11-23
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-11-23
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-11-23
Clifford Wolf
Add Verilog "automatic" keyword (ignored in synthesis)
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2017-09-26
Clifford Wolf
Merge branch 'master' of https://github.com/combinatory...
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2017-09-25
Clifford Wolf
Fix ignoring of simulation timings so that invalid...
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2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
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2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
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2017-02-24
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-23
Clifford Wolf
Add support for SystemVerilog unique, unique0, and...
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2017-02-23
Clifford Wolf
Added SystemVerilog support for ++ and --
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2017-02-11
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
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2017-02-09
Clifford Wolf
Add checker support to verilog front-end
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2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-08
Clifford Wolf
Add SV "rand" and "const rand" support
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2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
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2017-01-31
Clifford Wolf
Merge branch 'opt_compare_pr' of https://github.com...
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2017-01-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-01-17
Clifford Wolf
Add "enum" and "typedef" lexer support
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2016-08-28
Clifford Wolf
Removed $predict again
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2016-08-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-08-26
Clifford Wolf
Merge pull request #215 from frznchckn/to_upstream
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2016-08-26
Clifford Wolf
Added read_verilog -norestrict -assume-asserts
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2016-08-24
Clifford Wolf
Added SV "restrict" keyword
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2016-07-21
Clifford Wolf
After reading the SV spec, using non-standard predict...
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2016-07-13
Clifford Wolf
Added basic support for $expect cells
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-06-19
Clifford Wolf
Merge branch 'sv_packages' of https://github.com/rubund...
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2016-06-18
Ruben Undheim
Added support for SystemVerilog packages with localpara...
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-10-13
Clifford Wolf
SystemVerilog also has assume(), added implicit -D...
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2015-09-23
Clifford Wolf
Fixed support for $write system task
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2015-08-14
Larry Doolittle
Another block of spelling fixes
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2015-08-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-08-12
Clifford Wolf
Adjust makefiles to work with out-of-tree builds
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-03-25
Clifford Wolf
Ignore celldefine directive in verilog front-end
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2015-02-26
Clifford Wolf
Added non-std verilog assume() statement
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2015-02-14
Clifford Wolf
Fixed handling of "//" in filenames in verilog pre...
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2015-01-15
Clifford Wolf
Ignoring more system task and functions
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2014-12-27
Clifford Wolf
Improved some warning messages
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2014-11-24
Clifford Wolf
Fixed minor bug in parsing delays
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2014-11-24
Clifford Wolf
Fixed two minor bugs in constant parsing
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2014-11-09
Clifford Wolf
Added log_warning() API
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2014-10-23
Clifford Wolf
Re-introduced Yosys::readsome() helper function
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2014-10-14
Clifford Wolf
Merge branch 'win32'
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2014-10-14
William Speirs
Updated lexers & parsers to include prefixes
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