Add support for SVA "final" keyword
[yosys.git] / frontends / verilog / verilog_lexer.l
2019-05-04 Clifford WolfAdd support for SVA "final" keyword
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff
2019-03-11 Eddie HungMerge pull request #864 from YosysHQ/svalabelfix
2019-03-10 Clifford WolfFix handling of cases that look like sva labels, fixes...
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-09 Clifford WolfAlso add support for labels on sva module items, fixes...
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire
2019-01-05 Clifford WolfBugfix in Verilog string handling
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect
2018-10-16 argamaignore protect endprotect
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master
2018-08-27 Jim LawsonMerge branch 'master' into firrtl+modules+shiftfixes
2018-08-27 Jim LawsonMerge pull request #3 from YosysHQ/master
2018-08-27 Clifford WolfAdd "make coverage"
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file...
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-05-04 Clifford WolfMerge pull request #537 from mithro/yosys-vpr
2018-05-03 Dan GisselquistSupport more character literals
2018-03-27 Udi FinkelsteinFirst draft of Verilog parser support for specify block...
2018-03-11 Udi FinkelsteinThis PR should be the base for discussion, do not merge...
2017-11-28 Clifford WolfMerge pull request #462 from daveshah1/up5k
2017-11-24 Clifford WolfMerge pull request #446 from mithro/travis-rework
2017-11-23 Clifford WolfMerge branch 'master' into btor-ng
2017-11-23 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-11-23 Clifford WolfAdd Verilog "automatic" keyword (ignored in synthesis)
2017-09-26 Clifford WolfMerge branch 'master' of https://github.com/combinatory...
2017-09-25 Clifford WolfFix ignoring of simulation timings so that invalid...
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-23 Clifford WolfAdd support for SystemVerilog unique, unique0, and...
2017-02-23 Clifford WolfAdded SystemVerilog support for ++ and --
2017-02-11 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Clifford WolfAdd checker support to verilog front-end
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-08 Clifford WolfAdd SV "rand" and "const rand" support
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2017-01-31 Clifford WolfMerge branch 'opt_compare_pr' of https://github.com...
2017-01-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-01-17 Clifford WolfAdd "enum" and "typedef" lexer support
2016-08-28 Clifford WolfRemoved $predict again
2016-08-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-08-26 Clifford WolfMerge pull request #215 from frznchckn/to_upstream
2016-08-26 Clifford WolfAdded read_verilog -norestrict -assume-asserts
2016-08-24 Clifford WolfAdded SV "restrict" keyword
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund...
2016-06-18 Ruben UndheimAdded support for SystemVerilog packages with localpara...
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-13 Clifford WolfSystemVerilog also has assume(), added implicit -D...
2015-09-23 Clifford WolfFixed support for $write system task
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-12 Clifford WolfAdjust makefiles to work with out-of-tree builds
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-03-25 Clifford WolfIgnore celldefine directive in verilog front-end
2015-02-26 Clifford WolfAdded non-std verilog assume() statement
2015-02-14 Clifford WolfFixed handling of "//" in filenames in verilog pre...
2015-01-15 Clifford WolfIgnoring more system task and functions
2014-12-27 Clifford WolfImproved some warning messages
2014-11-24 Clifford WolfFixed minor bug in parsing delays
2014-11-24 Clifford WolfFixed two minor bugs in constant parsing
2014-11-09 Clifford WolfAdded log_warning() API
2014-10-23 Clifford WolfRe-introduced Yosys::readsome() helper function
2014-10-14 Clifford WolfMerge branch 'win32'
2014-10-14 William SpeirsUpdated lexers & parsers to include prefixes