Fix width detection of memory access with bit slice, fixes #974
[yosys.git] / frontends / verilog /
2019-04-30 Clifford WolfMerge pull request #972 from YosysHQ/clifford/fix968
2019-04-30 Clifford WolfMerge pull request #966 from YosysHQ/clifford/fix956
2019-04-30 Clifford WolfMerge branch 'master' into eddie/refactor_synth_xilinx
2019-04-30 Clifford WolfMerge pull request #973 from christian-krieg/feature...
2019-04-30 Clifford WolfInclude filename in "Executing Verilog-2005 frontend...
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #916 from YosysHQ/map_cells_before_m...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-22 Clifford WolfMerge pull request #945 from YosysHQ/clifford/libwb
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Clifford WolfNew behavior for front-end handling of whiteboxes
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-02 Eddie HungMerge pull request #895 from YosysHQ/pmux2shiftx
2019-03-29 Clifford WolfMerge pull request #907 from YosysHQ/clifford/fix906
2019-03-29 Clifford WolfBuild Verilog parser with -DYYMAXDEPTH=100000, fixes...
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-21 Clifford WolfImprove read_verilog debug output capabilities
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff
2019-03-11 Eddie HungMerge pull request #864 from YosysHQ/svalabelfix
2019-03-10 Clifford WolfFix handling of cases that look like sva labels, fixes...
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-09 Clifford WolfAlso add support for labels on sva module items, fixes...
2019-03-07 Clifford WolfAdd support for SVA labels in read_verilog
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire
2019-01-05 Clifford WolfBugfix in Verilog string handling
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737
2018-12-14 Sylvain Munautverilog_parser: Properly handle recursion when processi...
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-04 Clifford WolfAdd warning for SV "restrict" without "property"
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master
2018-10-25 Clifford WolfFix minor typo in error message
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the...
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-16 argamaignore protect endprotect
2018-10-13 Ruben UndheimHandle FIXME for modport members without type directly...
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master
2018-09-30 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-28 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-24 Clifford WolfAdd "read_verilog -noassert -noassume -assert-assumes"
2018-09-23 Clifford WolfAdded support for ommited "parameter" in Verilog-2001...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master
2018-08-27 Jim LawsonMerge branch 'master' into firrtl+modules+shiftfixes
2018-08-27 Jim LawsonMerge pull request #3 from YosysHQ/master
2018-08-27 Clifford WolfAdd "make coverage"
2018-08-23 Clifford WolfMerge pull request #610 from udif/udif_specify_round2
2018-08-23 Clifford WolfMerge pull request #614 from udif/pr_disable_dump_ptr
2018-08-23 Udi FinkelsteinAdded -no_dump_ptr flag for AST dump options in 'read_v...
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-20 Udi FinkelsteinFixed all known specify/endspecify issues, without...
2018-08-19 Udi FinkelsteinYosys can now parse https://github.com/verilog-to-routi...
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Udi FinkelsteinA few minor enhancements to specify block parsing.
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file...
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-07-20 Clifford WolfMerge pull request #586 from hzeller/more-sourcepos...
2018-07-20 Henner ZellerConvert more log_error() to log_file_error() where...
2018-07-20 Clifford WolfMerge pull request #585 from hzeller/use-file-warning...
2018-07-20 Henner ZellerUse log_file_warning(), log_file_error() functions.
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