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Add upto and offset to JSON ports
[yosys.git]
/
frontends
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verilog
/
2019-03-12
Clifford Wolf
Merge pull request #866 from YosysHQ/clifford/idstuff
tree
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commitdiff
2019-03-11
Eddie Hung
Merge pull request #864 from YosysHQ/svalabelfix
tree
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commitdiff
2019-03-10
Clifford Wolf
Fix handling of cases that look like sva labels, fixes...
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commitdiff
2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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commitdiff
2019-03-09
Clifford Wolf
Merge pull request #858 from YosysHQ/clifford/svalabels
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commitdiff
2019-03-09
Clifford Wolf
Also add support for labels on sva module items, fixes...
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commitdiff
2019-03-07
Clifford Wolf
Add support for SVA labels in read_verilog
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commitdiff
2019-02-11
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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commitdiff
2019-01-07
Clifford Wolf
Merge pull request #782 from whitequark/flowmap_dfs
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commitdiff
2019-01-06
Clifford Wolf
Merge pull request #780 from phire/rename_from_wire
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commitdiff
2019-01-05
Clifford Wolf
Bugfix in Verilog string handling
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
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commitdiff
2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
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commitdiff
2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
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commitdiff
2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #736 from whitequark/select_assert_list
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #704 from webhat/feature/fix-awk
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commitdiff
2018-12-16
Clifford Wolf
Merge pull request #738 from smunaut/issue_737
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commitdiff
2018-12-14
Sylvain Munaut
verilog_parser: Properly handle recursion when processi...
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commitdiff
2018-12-01
Clifford Wolf
Merge pull request #676 from rafaeltp/master
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commitdiff
2018-11-12
Clifford Wolf
Merge pull request #695 from daveshah1/ecp5_bb
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commitdiff
2018-11-04
Clifford Wolf
Add warning for SV "restrict" without "property"
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commitdiff
2018-10-25
Clifford Wolf
Merge pull request #678 from whentze/master
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commitdiff
2018-10-25
Clifford Wolf
Fix minor typo in error message
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commitdiff
2018-10-25
Clifford Wolf
Merge pull request #679 from udif/pr_syntax_error
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commitdiff
2018-10-24
Udi Finkelstein
Rename the generic "Syntax error" message from the...
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commitdiff
2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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commitdiff
2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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commitdiff
2018-10-18
Clifford Wolf
Merge pull request #657 from mithro/xilinx-vpr
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commitdiff
2018-10-18
Clifford Wolf
Merge pull request #664 from tklam/ignore-verilog-protect
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commitdiff
2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
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commitdiff
2018-10-16
Clifford Wolf
Merge branch 'yosys-0.8-rc'
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commitdiff
2018-10-16
argama
ignore protect endprotect
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commitdiff
2018-10-13
Ruben Undheim
Handle FIXME for modport members without type directly...
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commitdiff
2018-10-12
Ruben Undheim
Support for 'modports' for System Verilog interfaces
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commitdiff
2018-10-12
Ruben Undheim
Synthesis support for SystemVerilog interfaces
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commitdiff
2018-10-08
Clifford Wolf
Add "read_verilog -noassert -noassume -assert-assumes"
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commitdiff
2018-10-08
Clifford Wolf
Added support for ommited "parameter" in Verilog-2001...
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commitdiff
2018-10-02
Clifford Wolf
Merge pull request #645 from daveshah1/ecp5_dram_fix
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commitdiff
2018-10-01
Aman Goel
Merge pull request #4 from YosysHQ/master
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commitdiff
2018-09-30
Clifford Wolf
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
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commitdiff
2018-09-28
Clifford Wolf
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
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commitdiff
2018-09-24
Clifford Wolf
Add "read_verilog -noassert -noassume -assert-assumes"
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commitdiff
2018-09-23
Clifford Wolf
Added support for ommited "parameter" in Verilog-2001...
tree
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commitdiff
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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commitdiff
2018-09-14
Clifford Wolf
Merge pull request #625 from aman-goel/master
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commitdiff
2018-08-27
Jim Lawson
Merge branch 'master' into firrtl+modules+shiftfixes
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commitdiff
2018-08-27
Jim Lawson
Merge pull request #3 from YosysHQ/master
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commitdiff
2018-08-27
Clifford Wolf
Add "make coverage"
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commitdiff
2018-08-23
Clifford Wolf
Merge pull request #610 from udif/udif_specify_round2
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commitdiff
2018-08-23
Clifford Wolf
Merge pull request #614 from udif/pr_disable_dump_ptr
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commitdiff
2018-08-23
Udi Finkelstein
Added -no_dump_ptr flag for AST dump options in 'read_v...
tree
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commitdiff
2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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commitdiff
2018-08-20
Udi Finkelstein
Fixed all known specify/endspecify issues, without...
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commitdiff
2018-08-19
Udi Finkelstein
Yosys can now parse https://github.com/verilog-to-routi...
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commitdiff
2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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commitdiff
2018-08-15
Udi Finkelstein
A few minor enhancements to specify block parsing.
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #590 from hzeller/remaining-file...
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #576 from cr1901/no-resource
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #592 from japm48/master
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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commitdiff
2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
tree
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commitdiff
2018-07-20
Clifford Wolf
Merge pull request #586 from hzeller/more-sourcepos...
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commitdiff
2018-07-20
Henner Zeller
Convert more log_error() to log_file_error() where...
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commitdiff
2018-07-20
Clifford Wolf
Merge pull request #585 from hzeller/use-file-warning...
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commitdiff
2018-07-20
Henner Zeller
Use log_file_warning(), log_file_error() functions.
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commitdiff
2018-07-04
Aman Goel
Merge branch 'YosysHQ-master'
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commitdiff
2018-07-04
Aman Goel
Merging with official repo
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commitdiff
2018-06-06
Udi Finkelstein
Detect illegal port declaration, e.g input/output/inout...
tree
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commitdiff
2018-06-05
Udi Finkelstein
Modified errors into warnings
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commitdiff
2018-05-17
Clifford Wolf
Merge pull request #550 from jimparis/yosys-upstream
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commitdiff
2018-05-17
Jim Paris
Support SystemVerilog `` extension for macros
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commitdiff
2018-05-17
Jim Paris
Skip spaces around macro arguments
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commitdiff
2018-05-04
Clifford Wolf
Merge pull request #537 from mithro/yosys-vpr
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commitdiff
2018-05-03
Clifford Wolf
Replace -ignore_redef with -[no]overwrite
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commitdiff
2018-05-03
Dan Gisselquist
Support more character literals
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commitdiff
2018-04-13
Clifford Wolf
Add statement labels for immediate assertions
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commitdiff
2018-04-12
Clifford Wolf
Allow "property" in immediate assertions
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commitdiff
2018-04-06
Clifford Wolf
Add read_verilog anyseq/anyconst/allseq/allconst attrib...
tree
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commitdiff
2018-03-27
Udi Finkelstein
First draft of Verilog parser support for specify block...
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commitdiff
2018-03-11
Udi Finkelstein
This PR should be the base for discussion, do not merge...
tree
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commitdiff
2018-02-23
Clifford Wolf
Merge branch 'forall'
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commitdiff
2018-02-23
Clifford Wolf
Add $allconst and $allseq cell types
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commitdiff
2018-01-07
Clifford Wolf
Add support for "yosys -E"
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commitdiff
2017-12-24
Clifford Wolf
Bugfix in verilog_defaults argument parser
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commitdiff
2017-11-28
Clifford Wolf
Merge pull request #462 from daveshah1/up5k
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commitdiff
2017-11-24
Clifford Wolf
Merge pull request #446 from mithro/travis-rework
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commitdiff
2017-11-23
Clifford Wolf
Merge branch 'master' into btor-ng
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commitdiff
2017-11-23
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2017-11-23
Clifford Wolf
Add Verilog "automatic" keyword (ignored in synthesis)
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commitdiff
2017-11-18
Clifford Wolf
Merge pull request #455 from daveshah1/up5k
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commitdiff
2017-11-18
Clifford Wolf
Accept real-valued delay values
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