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Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV...
[yosys.git] / frontends / verilog /
2018-09-23 Clifford WolfAdded support for ommited "parameter" in Verilog-2001... tree | commitdiff
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master tree | commitdiff
2018-08-27 Jim LawsonMerge branch 'master' into firrtl+modules+shiftfixes tree | commitdiff
2018-08-27 Jim LawsonMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-27 Clifford WolfAdd "make coverage" tree | commitdiff
2018-08-23 Clifford WolfMerge pull request #610 from udif/udif_specify_round2 tree | commitdiff
2018-08-23 Clifford WolfMerge pull request #614 from udif/pr_disable_dump_ptr tree | commitdiff
2018-08-23 Udi FinkelsteinAdded -no_dump_ptr flag for AST dump options in 'read_v... tree | commitdiff
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-08-20 Udi FinkelsteinFixed all known specify/endspecify issues, without... tree | commitdiff
2018-08-19 Udi FinkelsteinYosys can now parse https://github.com/verilog-to-routi... tree | commitdiff
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-15 Udi FinkelsteinA few minor enhancements to specify block parsing. tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file... tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl tree | commitdiff
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in... tree | commitdiff
2018-07-20 Clifford WolfMerge pull request #586 from hzeller/more-sourcepos... tree | commitdiff
2018-07-20 Henner ZellerConvert more log_error() to log_file_error() where... tree | commitdiff
2018-07-20 Clifford WolfMerge pull request #585 from hzeller/use-file-warning... tree | commitdiff
2018-07-20 Henner ZellerUse log_file_warning(), log_file_error() functions. tree | commitdiff
2018-07-04 Aman GoelMerge branch 'YosysHQ-master' tree | commitdiff
2018-07-04 Aman GoelMerging with official repo tree | commitdiff
2018-06-06 Udi FinkelsteinDetect illegal port declaration, e.g input/output/inout... tree | commitdiff
2018-06-05 Udi FinkelsteinModified errors into warnings tree | commitdiff
2018-05-17 Clifford WolfMerge pull request #550 from jimparis/yosys-upstream tree | commitdiff
2018-05-17 Jim ParisSupport SystemVerilog `` extension for macros tree | commitdiff
2018-05-17 Jim ParisSkip spaces around macro arguments tree | commitdiff
2018-05-04 Clifford WolfMerge pull request #537 from mithro/yosys-vpr tree | commitdiff
2018-05-03 Clifford WolfReplace -ignore_redef with -[no]overwrite tree | commitdiff
2018-05-03 Dan GisselquistSupport more character literals tree | commitdiff
2018-04-13 Clifford WolfAdd statement labels for immediate assertions tree | commitdiff
2018-04-12 Clifford WolfAllow "property" in immediate assertions tree | commitdiff
2018-04-06 Clifford WolfAdd read_verilog anyseq/anyconst/allseq/allconst attrib... tree | commitdiff
2018-03-27 Udi FinkelsteinFirst draft of Verilog parser support for specify block... tree | commitdiff
2018-03-11 Udi FinkelsteinThis PR should be the base for discussion, do not merge... tree | commitdiff
2018-02-23 Clifford WolfMerge branch 'forall' tree | commitdiff
2018-02-23 Clifford WolfAdd $allconst and $allseq cell types tree | commitdiff
2018-01-07 Clifford WolfAdd support for "yosys -E" tree | commitdiff
2017-12-24 Clifford WolfBugfix in verilog_defaults argument parser tree | commitdiff
2017-11-28 Clifford WolfMerge pull request #462 from daveshah1/up5k tree | commitdiff
2017-11-24 Clifford WolfMerge pull request #446 from mithro/travis-rework tree | commitdiff
2017-11-23 Clifford WolfMerge branch 'master' into btor-ng tree | commitdiff
2017-11-23 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2017-11-23 Clifford WolfAdd Verilog "automatic" keyword (ignored in synthesis) tree | commitdiff
2017-11-18 Clifford WolfMerge pull request #455 from daveshah1/up5k tree | commitdiff
2017-11-18 Clifford WolfAccept real-valued delay values tree | commitdiff
2017-11-18 Clifford WolfMerge pull request #452 from cr1901/master tree | commitdiff
2017-11-14 William D. JonesAccommodate Windows-style paths during include-file... tree | commitdiff
2017-10-03 Clifford WolfMerge branch 'pr_ast_const_funcs' of https://github... tree | commitdiff
2017-10-03 Clifford WolfMerge branch 'fix_shift_reduce_conflict' of https:... tree | commitdiff
2017-09-30 Udi FinkelsteinResolved classical Bison IF/THEN/ELSE shift/reduce... tree | commitdiff
2017-09-26 Clifford WolfMerge branch 'vlogpp-inc-fixes' tree | commitdiff
2017-09-26 Clifford WolfMinor coding style fix tree | commitdiff
2017-09-26 Clifford WolfMerge branch 'master' of https://github.com/combinatory... tree | commitdiff
2017-09-25 Clifford WolfFix ignoring of simulation timings so that invalid... tree | commitdiff
2017-09-21 combinatorylogicAdding support for string macros and macros with argume... tree | commitdiff
2017-07-21 Clifford WolfAdd a paragraph about pre-defined macros to read_verilo... tree | commitdiff
2017-06-07 Clifford WolfFix generation of vlogtb output in yosys-smtbmc for... tree | commitdiff
2017-06-01 Clifford WolfFix handling of Verilog ~& and ~| operators tree | commitdiff
2017-04-30 Clifford WolfAdd support for localparam in module header tree | commitdiff
2017-04-26 Clifford WolfAdd support for `resetall compiler directive tree | commitdiff
2017-03-14 Clifford WolfFix verilog pre-processor for multi-level relative... tree | commitdiff
2017-03-01 Clifford WolfAllow $anyconst, etc. in non-formal SV mode tree | commitdiff
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj... tree | commitdiff
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event... tree | commitdiff
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2017-02-23 Clifford WolfAdd support for SystemVerilog unique, unique0, and... tree | commitdiff
2017-02-23 Clifford WolfAdded SystemVerilog support for ++ and -- tree | commitdiff
2017-02-11 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys... tree | commitdiff
2017-02-09 Clifford WolfAdd checker support to verilog front-end tree | commitdiff
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2017-02-08 Clifford WolfAdd SV "rand" and "const rand" support tree | commitdiff
2017-02-04 Clifford WolfFurther improve cover() support tree | commitdiff
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support tree | commitdiff
2017-01-31 Clifford WolfMerge branch 'opt_compare_pr' of https://github.com... tree | commitdiff
2017-01-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2017-01-17 Clifford WolfAdd "enum" and "typedef" lexer support tree | commitdiff
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master tree | commitdiff
2016-12-17 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys tree | commitdiff
2016-12-15 Clifford WolfAdded "verilog_defines" command tree | commitdiff
2016-11-28 Clifford WolfAdded support for macros as include file names tree | commitdiff
2016-11-28 Clifford WolfBugfix in "read_verilog -D NAME=VAL" handling tree | commitdiff
2016-11-15 Clifford WolfAdded support for hierarchical defparams tree | commitdiff
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v... tree | commitdiff
2016-10-14 Clifford WolfAdded $anyseq cell type tree | commitdiff
2016-08-30 Clifford WolfRemoved $aconst cell type tree | commitdiff
2016-08-28 Clifford WolfRemoved $predict again tree | commitdiff
2016-08-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2016-08-26 Clifford WolfMerge pull request #215 from frznchckn/to_upstream tree | commitdiff
2016-08-26 Clifford WolfAdded read_verilog -norestrict -assume-asserts tree | commitdiff
2016-08-25 Clifford WolfImproved verilog parser errors tree | commitdiff
2016-08-24 Clifford WolfAdded SV "restrict" keyword tree | commitdiff
2016-08-06 Clifford WolfFixed bug in parsing real constants tree | commitdiff
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