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Added new APIs to changelog
[yosys.git] / frontends /
2015-02-07 Clifford WolfIgnore explicit assignments to constants in HDL code tree | commitdiff
2015-02-07 Clifford WolfFixed a bug with autowire bit size tree | commitdiff
2015-01-24 Clifford WolfAdded ENABLE_NDEBUG makefile options tree | commitdiff
2015-01-15 Clifford WolfIgnoring more system task and functions tree | commitdiff
2015-01-15 Clifford WolfFixed handling of "input foo; reg [0:0] foo;" tree | commitdiff
2015-01-15 Clifford WolfConsolidate "Blocking assignment to memory.." msgs... tree | commitdiff
2015-01-08 Clifford WolfMerge pull request #46 from utzig/master tree | commitdiff
2015-01-08 Fabio UtzigEnable bison to be customized tree | commitdiff
2015-01-02 Clifford WolfDefine YOSYS and SYNTHESIS in preproc tree | commitdiff
2015-01-01 Clifford WolfFixed memory->start_offset handling tree | commitdiff
2014-12-29 Clifford WolfAdded global yosys_celltypes tree | commitdiff
2014-12-29 Clifford Wolfdict/pool changes in ast tree | commitdiff
2014-12-28 Clifford WolfChanged more code to dict<> and pool<> tree | commitdiff
2014-12-27 Clifford WolfImproved some warning messages tree | commitdiff
2014-12-27 Clifford WolfFixed mem2reg warning message tree | commitdiff
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types tree | commitdiff
2014-12-24 Clifford WolfRenamed extend() to extend_xx(), changed most users... tree | commitdiff
2014-12-11 Clifford WolfFixed supply0/supply1 with many wires tree | commitdiff
2014-11-24 Clifford WolfFixed minor bug in parsing delays tree | commitdiff
2014-11-24 Clifford WolfFixed two minor bugs in constant parsing tree | commitdiff
2014-11-14 Clifford WolfAdded warning for use of 'z' constants in HDL tree | commitdiff
2014-11-12 Clifford WolfFixed parsing of nested verilog concatenation and replicate tree | commitdiff
2014-11-09 Clifford WolfAdded log_warning() API tree | commitdiff
2014-11-08 Clifford WolfAdded "ENABLE_PLUGINS := 0" to verific amd64 build... tree | commitdiff
2014-10-30 Clifford WolfFixed parsing of "module mymod #( parameter foo = 1... tree | commitdiff
2014-10-29 Clifford WolfAST simplifier: optimize constant AST_CASE nodes before... tree | commitdiff
2014-10-27 Clifford WolfAdded support for task and function args in parentheses tree | commitdiff
2014-10-26 Clifford WolfImprovements in $readmem[bh] implementation tree | commitdiff
2014-10-26 Clifford WolfAdded support for $readmemh/$readmemb tree | commitdiff
2014-10-25 Clifford WolfFixed constant "cond ? string1 : string2" with strings... tree | commitdiff
2014-10-23 Clifford WolfRe-introduced Yosys::readsome() helper function tree | commitdiff
2014-10-19 Clifford Wolfminor indenting corrections tree | commitdiff
2014-10-19 Clifford WolfMerge pull request #40 from parvizp/compile_mac_10.9.2 tree | commitdiff
2014-10-19 Parviz PalangpourBuilds on Mac 10.9.2 with LLVM 3.5. tree | commitdiff
2014-10-18 Clifford WolfFixed various VS warnings tree | commitdiff
2014-10-17 William SpeirsHeader changes so it will compile on VS tree | commitdiff
2014-10-17 William SpeirsWrapped math in int constructor tree | commitdiff
2014-10-16 Clifford WolfPrint "SystemVerilog" in "read_verilog -sv" log messages tree | commitdiff
2014-10-15 Clifford WolfFixed handling of invalid array access in mem2reg code tree | commitdiff
2014-10-14 Clifford WolfMerge branch 'win32' tree | commitdiff
2014-10-14 Clifford WolfUpdated .gitignore file for ilang and verilog frontends tree | commitdiff
2014-10-14 Clifford WolfReplaced readsome() with read() and gcount() tree | commitdiff
2014-10-14 William SpeirsUpdated lexers & parsers to include prefixes tree | commitdiff
2014-10-12 Clifford WolfAdded make_temp_{file,dir}() and remove_directory(... tree | commitdiff
2014-10-12 Clifford WolfAdded run_command() api to replace system() and popen() tree | commitdiff
2014-10-11 Clifford WolfDo not the 'z' modifier in format string (another win32... tree | commitdiff
2014-10-11 Clifford WolfFixed win32 troubles with f.readsome() tree | commitdiff
2014-10-11 Clifford WolfDisabled vhdl2verilog command for win32 builds tree | commitdiff
2014-10-10 Clifford WolfAdded format __attribute__ to stringf() tree | commitdiff
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision... tree | commitdiff
2014-09-27 Clifford Wolfnamespace Yosys tree | commitdiff
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... tree | commitdiff
2014-09-08 Clifford WolfAnother $clog2 bugfix tree | commitdiff
2014-09-06 Clifford WolfFixed $clog2 (off by one error) tree | commitdiff
2014-09-06 Clifford WolfFixed assignment of out-of bounds array element tree | commitdiff
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master tree | commitdiff
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian tree | commitdiff
2014-09-04 Clifford WolfRemoved $bu0 cell type tree | commitdiff
2014-08-23 Clifford WolfRemoved compatbility.{h,cc}: Not using open_memstream... tree | commitdiff
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream tree | commitdiff
2014-08-22 Clifford WolfAdded emscripten (emcc) support to build system and... tree | commitdiff
2014-08-22 Clifford WolfAdded support for non-standard <plugin>:<c_name> DPI... tree | commitdiff
2014-08-22 Clifford WolfArchibald Rust and Clifford Wolf: ffi-based dpi_call() tree | commitdiff
2014-08-21 Clifford WolfFixed small memory leak in ast simplify tree | commitdiff
2014-08-21 Clifford WolfAdded support for DPI function with different names... tree | commitdiff
2014-08-21 Clifford WolfAdded AstNode::asInt() tree | commitdiff
2014-08-21 Clifford WolfFixed memory leak in DPI function calls tree | commitdiff
2014-08-21 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys tree | commitdiff
2014-08-21 Clifford WolfAdded Verilog/AST support for DPI functions (dpi_call... tree | commitdiff
2014-08-21 Clifford WolfAdded support for global tasks and functions tree | commitdiff
2014-08-18 Clifford WolfAdded "via_celltype" attribute on task/func tree | commitdiff
2014-08-17 Clifford WolfAdded const folding of AST_CASE to AST simplifier tree | commitdiff
2014-08-17 Clifford WolfImproved AST ProcessGenerator performance tree | commitdiff
2014-08-16 Clifford WolfUse stackmap<> in AST ProcessGenerator tree | commitdiff
2014-08-16 Clifford WolfAdded module->uniquify() tree | commitdiff
2014-08-16 Clifford WolfAST ProcessGenerator: replaced subst_*_{from,to} with... tree | commitdiff
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_ tree | commitdiff
2014-08-14 Clifford WolfFixed bug in "read_verilog -ignore_redef" tree | commitdiff
2014-08-14 Clifford WolfAdded RTLIL::SigSpec::to_sigbit_map() tree | commitdiff
2014-08-14 Clifford WolfChanged the AST genWidthRTLIL subst interface to use... tree | commitdiff
2014-08-14 Clifford WolfFixed line numbers when using here-doc macros tree | commitdiff
2014-08-14 Clifford WolfFixed handling of task outputs tree | commitdiff
2014-08-14 Clifford WolfAdded module->ports tree | commitdiff
2014-08-13 Clifford WolfAdded support for non-standard """ macro bodies tree | commitdiff
2014-08-12 Clifford WolfFixed building verific bindings tree | commitdiff
2014-08-07 Clifford WolfAlso allow "module foobar(input foo, output bar, .... tree | commitdiff
2014-08-06 Clifford WolfAdded AST_MULTIRANGE (arrays with more than 1 dimension) tree | commitdiff
2014-08-05 Clifford WolfImproved scope resolution of local regs in Verilog... tree | commitdiff
2014-08-05 Clifford WolfFixed AST handling of variables declared inside a funct... tree | commitdiff
2014-08-04 Clifford WolfAdded support for non-standard "module mod_name(..... tree | commitdiff
2014-08-02 Clifford WolfMore bugfixes related to new RTLIL::IdString tree | commitdiff
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage tree | commitdiff
2014-08-01 Clifford WolfPreparations for RTLIL::IdString redesign: cleanup... tree | commitdiff
2014-08-01 Clifford WolfReplaced sha1 implementation tree | commitdiff
2014-07-31 Clifford WolfFixed build of verific bindings tree | commitdiff
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added... tree | commitdiff
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module... tree | commitdiff
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys... tree | commitdiff
2014-07-30 Clifford WolfFixed counting verilog line numbers for "// synopsys... tree | commitdiff
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