2017-07-28 |
Clifford Wolf | Add merging of "past FFs" to verific importer |
tree | commitdiff |
2017-07-28 |
Clifford Wolf | Add minimal support for PSL in VHDL via Verific |
tree | commitdiff |
2017-07-28 |
Clifford Wolf | Improve Verific HDL language options |
tree | commitdiff |
2017-07-28 |
Clifford Wolf | Fix handling of non-user-declared Verific netbus |
tree | commitdiff |
2017-07-27 |
Clifford Wolf | Improve Verific SVA importer |
tree | commitdiff |
2017-07-27 |
Clifford Wolf | Add log_warning_noprefix() API, Use for Verific warning... |
tree | commitdiff |
2017-07-27 |
Clifford Wolf | Add "verific -import -n" and "verific -import -nosva" |
tree | commitdiff |
2017-07-27 |
Clifford Wolf | Improve Verific SVA import: negedge and $past |
tree | commitdiff |
2017-07-27 |
Clifford Wolf | Improve Verific SVA importer |
tree | commitdiff |
2017-07-26 |
Clifford Wolf | Improve Verific bindings (mostly related to SVA) |
tree | commitdiff |
2017-07-25 |
Clifford Wolf | Improve "help verific" message |
tree | commitdiff |
2017-07-25 |
Clifford Wolf | Add "verific -extnets" |
tree | commitdiff |
2017-07-25 |
Clifford Wolf | Improve "verific -all" handling |
tree | commitdiff |
2017-07-24 |
Clifford Wolf | Add "verific -import -d <dump_file" |
tree | commitdiff |
2017-07-24 |
Clifford Wolf | Add "verific -import -flatten" and "verific -import -v" |
tree | commitdiff |
2017-07-22 |
Clifford Wolf | Add "verific -import -k" |
tree | commitdiff |
2017-07-22 |
Clifford Wolf | Improve docs for verific bindings, add simply sby example |
tree | commitdiff |
2017-07-21 |
Clifford Wolf | Fix "read_blif -wideports" handling of cells with wide... |
tree | commitdiff |
2017-07-21 |
Clifford Wolf | Add a paragraph about pre-defined macros to read_verilo... |
tree | commitdiff |
2017-07-10 |
Clifford Wolf | Add attributes and parameter support to JSON front-end |
tree | commitdiff |
2017-07-08 |
Clifford Wolf | Add JSON front-end |
tree | commitdiff |
2017-07-04 |
Clifford Wolf | Add Verific Release information to log |
tree | commitdiff |
2017-06-07 |
Clifford Wolf | Fix generation of vlogtb output in yosys-smtbmc for... |
tree | commitdiff |
2017-06-01 |
Clifford Wolf | Fix handling of Verilog ~& and ~| operators |
tree | commitdiff |
2017-04-30 |
Clifford Wolf | Add support for localparam in module header |
tree | commitdiff |
2017-04-26 |
Clifford Wolf | Add support for `resetall compiler directive |
tree | commitdiff |
2017-03-14 |
Clifford Wolf | Fix verilog pre-processor for multi-level relative... |
tree | commitdiff |
2017-03-01 |
Clifford Wolf | Allow $anyconst, etc. in non-formal SV mode |
tree | commitdiff |
2017-02-25 |
Clifford Wolf | Merge branch 'master' of https://github.com/klammerj... |
tree | commitdiff |
2017-02-25 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
tree | commitdiff |
2017-02-25 |
Clifford Wolf | Add $live and $fair cell types, add support for s_event... |
tree | commitdiff |
2017-02-24 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-02-23 |
Clifford Wolf | Add support for SystemVerilog unique, unique0, and... |
tree | commitdiff |
2017-02-23 |
Clifford Wolf | Preserve string parameters |
tree | commitdiff |
2017-02-23 |
Clifford Wolf | Added SystemVerilog support for ++ and -- |
tree | commitdiff |
2017-02-14 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-02-14 |
Clifford Wolf | Fix incorrect "incompatible re-declaration of wire... |
tree | commitdiff |
2017-02-11 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Add support for verific mem initialization |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Fix another stupid bug in the same line |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Add verific support for initialized variables |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Improve handling of Verific warnings and error messages |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Fix extremely stupid typo |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Merge branch 'master' of https://github.com/stv0g/yosys... |
tree | commitdiff |
2017-02-09 |
Clifford Wolf | Add checker support to verilog front-end |
tree | commitdiff |
2017-02-09 |
Clifford Wolf | Add "rand" and "rand const" verific support |
tree | commitdiff |
2017-02-09 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-02-08 |
Clifford Wolf | Add SV "rand" and "const rand" support |
tree | commitdiff |
2017-02-08 |
Clifford Wolf | Add PSL parser mode to verific front-end |
tree | commitdiff |
2017-02-06 |
Clifford Wolf | Add "read_blif -wideports" |
tree | commitdiff |
2017-02-04 |
Clifford Wolf | Further improve cover() support |
tree | commitdiff |
2017-02-04 |
Clifford Wolf | Add $cover cell type and SVA cover() support |
tree | commitdiff |
2017-02-04 |
Clifford Wolf | Add assert/assume support to verific front-end |
tree | commitdiff |
2017-01-31 |
Clifford Wolf | Merge branch 'opt_compare_pr' of https://github.com... |
tree | commitdiff |
2017-01-26 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
tree | commitdiff |
2017-01-17 |
Clifford Wolf | Add "enum" and "typedef" lexer support |
tree | commitdiff |
2017-01-15 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-01-15 |
Clifford Wolf | Fix bug in AstNode::mem2reg_as_needed_pass2() |
tree | commitdiff |
2017-01-05 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-01-05 |
Clifford Wolf | Fixed handling of local memories in functions |
tree | commitdiff |
2017-01-04 |
Clifford Wolf | Added handling of local memories and error for local... |
tree | commitdiff |
2017-01-03 |
Clifford Wolf | Added Verilog $rtoi and $itor support |
tree | commitdiff |
2016-12-23 |
Andrew Zonenberg | Merge pull request #1 from azonenberg-hk/master |
tree | commitdiff |
2016-12-17 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2016-12-15 |
Clifford Wolf | Added "verilog_defines" command |
tree | commitdiff |
2016-11-28 |
Clifford Wolf | Added support for macros as include file names |
tree | commitdiff |
2016-11-28 |
Clifford Wolf | Bugfix in "read_verilog -D NAME=VAL" handling |
tree | commitdiff |
2016-11-15 |
Clifford Wolf | Added support for hierarchical defparams |
tree | commitdiff |
2016-11-15 |
Clifford Wolf | Remember global declarations and defines accross read_v... |
tree | commitdiff |
2016-11-04 |
Clifford Wolf | Fixed anonymous genblock object names |
tree | commitdiff |
2016-11-01 |
Clifford Wolf | Some fixes in handling of signed arrays |
tree | commitdiff |
2016-10-22 |
Clifford Wolf | Added avail params to ilang format, check module params... |
tree | commitdiff |
2016-10-19 |
Clifford Wolf | No limit for length of lines in BLIF front-end |
tree | commitdiff |
2016-10-14 |
Clifford Wolf | Added $anyseq cell type |
tree | commitdiff |
2016-10-14 |
Clifford Wolf | Added $global_clock verilog syntax support for creating... |
tree | commitdiff |
2016-10-11 |
Clifford Wolf | Added $ff and $_FF_ cell types |
tree | commitdiff |
2016-09-23 |
Clifford Wolf | Added liberty parser support for types within cell... |
tree | commitdiff |
2016-09-23 |
Clifford Wolf | Merge branch 'master' of https://github.com/brouhaha... |
tree | commitdiff |
2016-09-18 |
Clifford Wolf | Added $past, $stable, $rose, $fell SVA functions |
tree | commitdiff |
2016-09-18 |
Clifford Wolf | Added support for bus interfaces to "read_liberty ... |
tree | commitdiff |
2016-09-06 |
Clifford Wolf | Added assertpmux |
tree | commitdiff |
2016-09-06 |
Clifford Wolf | Bugfix in parsing of BLIF latch init values |
tree | commitdiff |
2016-09-06 |
Clifford Wolf | Avoid creation of bogus initial blocks for assert/assum... |
tree | commitdiff |
2016-08-30 |
Clifford Wolf | Added $anyconst support to yosys-smtbmc |
tree | commitdiff |
2016-08-30 |
Clifford Wolf | Removed $aconst cell type |
tree | commitdiff |
2016-08-28 |
Clifford Wolf | Removed $predict again |
tree | commitdiff |
2016-08-26 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
tree | commitdiff |
2016-08-26 |
Clifford Wolf | Merge pull request #215 from frznchckn/to_upstream |
tree | commitdiff |
2016-08-26 |
Clifford Wolf | Added read_verilog -norestrict -assume-asserts |
tree | commitdiff |
2016-08-25 |
Clifford Wolf | Improved verilog parser errors |
tree | commitdiff |
2016-08-24 |
Clifford Wolf | Added SV "restrict" keyword |
tree | commitdiff |
2016-08-22 |
Clifford Wolf | Fixed bug with memories that do not have a down-to... |
tree | commitdiff |
2016-08-21 |
Clifford Wolf | Another bugfix in mem2reg code |
tree | commitdiff |
2016-08-21 |
Clifford Wolf | Minor improvements to AstNode::dumpAst() and AstNode... |
tree | commitdiff |
2016-08-20 |
Clifford Wolf | Fixed finish_addr handling in $readmemh/$readmemb |
tree | commitdiff |
2016-08-19 |
Clifford Wolf | Optimize memory address port width in wreduce and memor... |
tree | commitdiff |
2016-08-10 |
Clifford Wolf | Only allow posedge/negedge with 1 bit wide signals |
tree | commitdiff |
2016-08-06 |
Clifford Wolf | Fixed bug in parsing real constants |
tree | commitdiff |
2016-07-30 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
tree | commitdiff |
2016-07-27 |
Clifford Wolf | Added $anyconst and $aconst |
tree | commitdiff |
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