Try way that doesn't involve creating a new wire
[yosys.git] / frontends /
2019-06-08 Clifford WolfMerge pull request #1078 from YosysHQ/eddie/muxcover_costs
2019-06-07 Eddie HungFix spacing from spaces to tabs
2019-06-07 Clifford WolfMerge pull request #1079 from YosysHQ/eddie/fix_read_aiger
2019-06-07 Eddie HungFix spacing (entire file is wrong anyway, will fix...
2019-06-07 Eddie HungRemove unnecessary std::getline() for ASCII
2019-06-07 Eddie HungFix read_aiger -- create zero driver, fix init width...
2019-06-07 Clifford WolfMerge pull request #1077 from YosysHQ/clifford/pr983
2019-06-07 Clifford WolfFixes and cleanups in AST_TECALL handling
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-06-07 Clifford WolfMerge branch 'tux3-implicit_named_connection'
2019-06-07 Clifford WolfCleanup tux3-implicit_named_connection
2019-06-07 Clifford WolfMerge branch 'implicit_named_connection' of https:...
2019-06-06 tux3SystemVerilog support for implicit named port connections
2019-06-06 Clifford WolfMerge pull request #1060 from antmicro/parsing_attr_on_...
2019-06-06 David ShahMerge pull request #1073 from whitequark/ecp5-diamond-iob
2019-06-05 Maciej KurcFixed memory leak.
2019-06-05 Clifford WolfMerge pull request #999 from jakobwenzel/setundefInitFix
2019-06-02 Clifford WolfOnly support Symbiotic EDA flavored Verific
2019-05-31 Maciej KurcAdded support for parsing attributes on port connections.
2019-05-30 Clifford WolfEnable Verific flag veri_elaborate_top_level_modules_ha...
2019-05-28 Clifford WolfMerge pull request #1049 from YosysHQ/clifford/fix1047
2019-05-28 Clifford WolfMerge pull request #1050 from YosysHQ/clifford/wandwor
2019-05-28 Clifford WolfMerge branch 'wandwor' of https://github.com/thasti...
2019-05-27 Stefan BiereigelMerge branch 'master' into wandwor
2019-05-27 Stefan Biereigelremove leftovers from ast data structures
2019-05-27 Stefan Biereigelmove wand/wor resolution into hierarchy pass
2019-05-27 Clifford WolfMerge pull request #1044 from mmicko/invalid_width_range
2019-05-27 Clifford WolfMerge pull request #1043 from mmicko/unsized_constant
2019-05-27 Miodrag MilanovicGive error instead of asserting for invalid range,...
2019-05-27 Miodrag MilanovicAdded support for unsized constants, fixes #1022
2019-05-23 Stefan Biereigelfix assignment of non-wires
2019-05-23 Stefan Biereigelfix indentation across files
2019-05-23 Stefan Biereigelimplementation for assignments working
2019-05-23 Stefan Biereigelmake lexer/parser aware of wand/wor net types
2019-05-22 Clifford WolfMerge pull request #1019 from YosysHQ/clifford/fix1016
2019-05-22 Clifford WolfMerge pull request #1021 from ucb-bar/fixfirrtl_shr,neg
2019-05-22 Eddie HungMerge pull request #1024 from YosysHQ/eddie/fix_Wmissin...
2019-05-22 Eddie HungRename label
2019-05-22 Eddie HungTry again
2019-05-21 Eddie HungFix warning
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-18 Clifford WolfMerge pull request #1017 from Kmanfi/bigger_verilog_files
2019-05-18 Kaj TuomiRead bigger Verilog files.
2019-05-16 Clifford WolfMerge pull request #1013 from antmicro/parameter_attributes
2019-05-16 Maciej KurcAdded support for parsing attributes on parameters...
2019-05-15 Clifford WolfMerge pull request #1011 from hzeller/fix-constructing...
2019-05-15 Clifford WolfMerge pull request #1010 from hzeller/yacc-self-contained
2019-05-15 Henner ZellerMake the generated *.tab.hh include all the headers...
2019-05-08 Clifford WolfMerge pull request #991 from kristofferkoch/gcc9-warnings
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfMerge pull request #975 from YosysHQ/clifford/fix968
2019-05-06 Clifford WolfMerge pull request #871 from YosysHQ/verific_import
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-06 Clifford WolfFix the other bison warning in ilang_parser.y
2019-05-06 Clifford WolfMerge pull request #992 from bwidawsk/bison-fix
2019-05-06 Clifford WolfMerge pull request #989 from YosysHQ/dave/abc_name_improve
2019-05-06 Clifford WolfAdd "real" keyword to ilang format
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-06 Ben Widawskyverilog_parser: Fix Bison warning
2019-05-04 Clifford WolfMerge pull request #988 from YosysHQ/clifford/fix987
2019-05-04 Clifford WolfAdd support for SVA "final" keyword
2019-05-04 Clifford WolfImprove write_verilog specify support
2019-05-04 Clifford WolfAdd approximate support for SV "var" keyword, fixes...
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Eddie HungFor hier_tree::Elaborate() also include SV root modules...
2019-05-03 Eddie HungFix verific_parameters construction, use attribute...
2019-05-03 Eddie HungWIP -chparam support for hierarchy when verific
2019-05-03 Eddie Hungverific_import() changes to avoid ElaborateAll()
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-03 Clifford WolfMerge pull request #984 from YosysHQ/eddie/fix_982
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
2019-05-03 Udi FinkelsteinInitial implementation of elaboration system tasks
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-05-01 Clifford WolfAdd splitcmplxassign test case and silence splitcmplxas...
2019-05-01 Clifford WolfFix width detection of memory access with bit slice...
2019-05-01 Clifford WolfRe-enable "final loop assignment" feature
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-04-30 Clifford WolfDisabled "final loop assignment" feature
2019-04-30 Clifford WolfMerge pull request #972 from YosysHQ/clifford/fix968
2019-04-30 Clifford WolfMerge pull request #966 from YosysHQ/clifford/fix956
2019-04-30 Clifford WolfMerge branch 'master' into eddie/refactor_synth_xilinx
2019-04-30 Clifford WolfMerge pull request #973 from christian-krieg/feature...
2019-04-30 Clifford WolfInclude filename in "Executing Verilog-2005 frontend...
2019-04-30 Clifford WolfAdd final loop variable assignment when unrolling for...
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
2019-04-23 Clifford WolfAllow $specify[23] cells in blackbox modules
2019-04-23 Clifford WolfRename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
2019-04-23 Clifford WolfChecking and fixing specify cells in genRTLIL
2019-04-23 Clifford WolfUn-break default specify parser
2019-04-23 Clifford WolfAdd specify parser
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl
2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370
2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfDetermine correct signedness and expression width in...
2019-04-22 Clifford WolfAdd log_debug() framework
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