Fix handling of partial init attributes in write_verilog, fixes #997
[yosys.git] / frontends /
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfMerge pull request #975 from YosysHQ/clifford/fix968
2019-05-06 Clifford WolfMerge pull request #871 from YosysHQ/verific_import
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-06 Clifford WolfFix the other bison warning in ilang_parser.y
2019-05-06 Clifford WolfMerge pull request #992 from bwidawsk/bison-fix
2019-05-06 Clifford WolfMerge pull request #989 from YosysHQ/dave/abc_name_improve
2019-05-06 Clifford WolfAdd "real" keyword to ilang format
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-06 Ben Widawskyverilog_parser: Fix Bison warning
2019-05-04 Clifford WolfMerge pull request #988 from YosysHQ/clifford/fix987
2019-05-04 Clifford WolfAdd support for SVA "final" keyword
2019-05-04 Clifford WolfImprove write_verilog specify support
2019-05-04 Clifford WolfAdd approximate support for SV "var" keyword, fixes...
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Eddie HungFor hier_tree::Elaborate() also include SV root modules...
2019-05-03 Eddie HungFix verific_parameters construction, use attribute...
2019-05-03 Eddie HungWIP -chparam support for hierarchy when verific
2019-05-03 Eddie Hungverific_import() changes to avoid ElaborateAll()
2019-05-03 Clifford WolfMerge pull request #969 from YosysHQ/clifford/pmgenstuff
2019-05-03 Clifford WolfMerge pull request #984 from YosysHQ/eddie/fix_982
2019-05-03 Clifford WolfMerge pull request #976 from YosysHQ/clifford/fix974
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-05-01 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-05-01 Clifford WolfAdd splitcmplxassign test case and silence splitcmplxas...
2019-05-01 Clifford WolfFix width detection of memory access with bit slice...
2019-05-01 Clifford WolfRe-enable "final loop assignment" feature
2019-04-30 Clifford WolfDisabled "final loop assignment" feature
2019-04-30 Clifford WolfMerge pull request #972 from YosysHQ/clifford/fix968
2019-04-30 Clifford WolfMerge pull request #966 from YosysHQ/clifford/fix956
2019-04-30 Clifford WolfMerge branch 'master' into eddie/refactor_synth_xilinx
2019-04-30 Clifford WolfMerge pull request #973 from christian-krieg/feature...
2019-04-30 Clifford WolfInclude filename in "Executing Verilog-2005 frontend...
2019-04-30 Clifford WolfAdd final loop variable assignment when unrolling for...
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
2019-04-23 Clifford WolfAllow $specify[23] cells in blackbox modules
2019-04-23 Clifford WolfRename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
2019-04-23 Clifford WolfChecking and fixing specify cells in genRTLIL
2019-04-23 Clifford WolfUn-break default specify parser
2019-04-23 Clifford WolfAdd specify parser
2019-04-22 Eddie HungMerge pull request #914 from YosysHQ/xc7srl
2019-04-22 Clifford WolfMerge pull request #952 from YosysHQ/clifford/fix370
2019-04-22 Clifford WolfMerge pull request #951 from YosysHQ/clifford/logdebug
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfDetermine correct signedness and expression width in...
2019-04-22 Clifford WolfAdd log_debug() framework
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #916 from YosysHQ/map_cells_before_m...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-22 Clifford WolfMerge pull request #945 from YosysHQ/clifford/libwb
2019-04-21 Eddie HungMerge branch 'master' into map_cells_before_map_luts
2019-04-21 Clifford WolfAdd "noblackbox" attribute
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/clifford/pmux2shif...
2019-04-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-20 Clifford WolfNew behavior for front-end handling of whiteboxes
2019-04-20 Clifford WolfMerge pull request #943 from YosysHQ/clifford/whitebox
2019-04-18 Clifford WolfAdd "whitebox" attribute, add "read_verilog -wb"
2019-04-09 Zachary Snowsupport repeat loops with constant repeat counts outsid...
2019-04-05 Eddie HungMerge branch 'eddie/fix_retime' into xc7srl
2019-04-05 Clifford WolfAdd "read_ilang -lib"
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-02 Eddie HungMerge pull request #895 from YosysHQ/pmux2shiftx
2019-03-29 Clifford WolfMerge pull request #907 from YosysHQ/clifford/fix906
2019-03-29 Clifford WolfBuild Verilog parser with -DYYMAXDEPTH=100000, fixes...
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-28 Clifford WolfMerge pull request #903 from YosysHQ/bram_reset_transp
2019-03-27 Clifford WolfAdd "read -verific" and "read -noverific"
2019-03-26 Clifford WolfFix "verific -extnets" for more complex situations
2019-03-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-22 Clifford WolfMerge pull request #889 from YosysHQ/clifford/fix888
2019-03-21 Clifford WolfFix mem2reg handling of memories with upto data ports...
2019-03-21 Clifford WolfImprove "read_verilog -dump_vlog[12]" handling of upto...
2019-03-21 Clifford WolfImprove read_verilog debug output capabilities
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMerge pull request #808 from eddiehung/read_aiger
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-19 Eddie HungAdd author name
2019-03-19 Clifford WolfMerge pull request #884 from zachjs/master
2019-03-19 Zachary Snowfix local name resolution in prefix constructs
2019-03-14 Clifford WolfMerge pull request #872 from YosysHQ/clifford/pmuxfix
2019-03-14 Clifford WolfImprove handling of "full_case" attributes
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 Clifford WolfMerge pull request #869 from cr1901/win-shell
2019-03-13 Clifford WolfMerge pull request #868 from YosysHQ/clifford/fixmem
2019-03-12 Clifford WolfMerge pull request #866 from YosysHQ/clifford/idstuff
2019-03-12 Clifford WolfImprove handling of memories used in mem index expressi...
2019-03-12 Clifford WolfRemove outdated "blocking assignment to memory" warning
2019-03-12 Clifford WolfOnly set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for...
2019-03-11 Eddie HungMerge pull request #864 from YosysHQ/svalabelfix
2019-03-10 Clifford WolfFix handling of cases that look like sva labels, fixes...
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-09 Clifford WolfMerge pull request #858 from YosysHQ/clifford/svalabels
2019-03-09 Clifford WolfMerge pull request #861 from YosysHQ/verific_chparam
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