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Fixed some typos
[yosys.git]
/
frontends
/
2016-03-24
Clifford Wolf
Do not set "nosync" on task outputs, fixes #134
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commitdiff
2016-03-21
Clifford Wolf
Added support for $stop system task
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commitdiff
2016-03-19
Clifford Wolf
Added $display %m support, fixed mem leak in $display...
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commitdiff
2016-03-18
Clifford Wolf
Fixed localparam signdness, fixes #127
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commitdiff
2016-03-18
Clifford Wolf
Set "nosync" attribute on internal task/function wires
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commitdiff
2016-03-15
Clifford Wolf
Fixed Verilog parser fix and more similar improvements
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commitdiff
2016-03-15
Andrew Becker
Use left-recursive rule for cell_port_list in Verilog...
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commitdiff
2016-03-11
Clifford Wolf
Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
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commitdiff
2016-03-10
Clifford Wolf
Fixed typos in verilog_defaults help message
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commitdiff
2016-02-24
Clifford Wolf
Fixed BLIF parser for empty port assignments
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commitdiff
2016-02-13
Clifford Wolf
Fixed some visual studio warnings
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commitdiff
2016-02-13
Clifford Wolf
Support for more Verific primitives (patch I got per...
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commitdiff
2016-02-03
Clifford Wolf
Bugfix in Verific front-end
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commitdiff
2016-02-02
Clifford Wolf
Updated verific build instructions
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commitdiff
2016-02-02
Clifford Wolf
Added addBufGate module method
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commitdiff
2016-01-31
Clifford Wolf
Merge branch 'rtlil_remove2_speedup' of https://github...
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commitdiff
2016-01-31
Rick Altherr
genrtlil: avoid converting SigSpec to set<SigBit> when...
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commitdiff
2015-12-20
Clifford Wolf
Various improvements in BLIF front-end
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commitdiff
2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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commitdiff
2015-11-29
Clifford Wolf
Fixed oom bug in ilang parser
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commitdiff
2015-11-27
Clifford Wolf
Fixed performance bug in ilang parser
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commitdiff
2015-11-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2015-11-24
Clifford Wolf
Added PRIM_DLATCHRS support to verific front-end
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commitdiff
2015-11-23
Clifford Wolf
Fixed handling of re-declarations of wires in tasks...
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commitdiff
2015-11-16
Clifford Wolf
Fixed performance bug in Verific importer
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commitdiff
2015-11-12
Clifford Wolf
Changes for Verific 3.16_484_32_151112
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commitdiff
2015-11-12
Clifford Wolf
More bugfixes in handling of parameters in tasks and...
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commitdiff
2015-11-11
Clifford Wolf
Fixed handling of parameters and localparams in functions
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commitdiff
2015-10-25
Clifford Wolf
Import more std:: stuff into Yosys namespace
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commitdiff
2015-10-15
Clifford Wolf
Fixed bug in verilog parser
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commitdiff
2015-10-13
Clifford Wolf
SystemVerilog also has assume(), added implicit -D...
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commitdiff
2015-10-07
Clifford Wolf
Added support for "parameter" and "localparam" in globa...
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commitdiff
2015-10-01
Clifford Wolf
Fixed complexity of assigning to vectors in constant...
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commitdiff
2015-09-30
Clifford Wolf
Fixed detection of unconditional $readmem[hb]
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commitdiff
2015-09-25
Clifford Wolf
Bugfixes in $readmem[hb]
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commitdiff
2015-09-25
Clifford Wolf
Fixed segfault in AstNode::asReal
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commitdiff
2015-09-25
Clifford Wolf
Added read-enable to memory model
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commitdiff
2015-09-24
Clifford Wolf
Fixed AstNode::mkconst_bits() segfault on zero-sized...
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commitdiff
2015-09-23
Clifford Wolf
Added read_verilog -nodpi
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commitdiff
2015-09-23
Clifford Wolf
Bugfix in handling of multi-dimensional memories
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commitdiff
2015-09-23
Clifford Wolf
Warning for $display/$write outside initial block
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commitdiff
2015-09-23
Clifford Wolf
Fixed support for $write system task
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commitdiff
2015-09-22
Clifford Wolf
Fixed detection of "task foo(bar);" syntax error
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commitdiff
2015-09-22
Clifford Wolf
Fixed multi-level prefix resolving
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commitdiff
2015-09-22
Clifford Wolf
Fixed segfault on invalid verilog constant 1'b_
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commitdiff
2015-09-19
Andrew Zonenberg
Improvements to $display system task
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commitdiff
2015-09-18
Clifford Wolf
Merge branch 'feat-finish-disp'
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commitdiff
2015-09-18
Clifford Wolf
Added AST_INITIAL checks for $finish and $display
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commitdiff
2015-09-18
Andrew Zonenberg
Initial implementation of $display()
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commitdiff
2015-09-18
Andrew Zonenberg
Initial implementation of $finish()
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commitdiff
2015-09-01
Clifford Wolf
gcc-4.6 build fixes
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commitdiff
2015-08-22
Clifford Wolf
Fixed handling of memory read without address
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commitdiff
2015-08-17
Clifford Wolf
Small corrections to const2ast warning messages
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commitdiff
2015-08-17
Florian Zeitz
Check base-n literals only contain valid digits
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commitdiff
2015-08-17
Florian Zeitz
Warn on literals exceeding the specified bit width
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commitdiff
2015-08-14
Larry Doolittle
Another block of spelling fixes
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commitdiff
2015-08-14
Larry Doolittle
Keep gcc from complaining about uninitialized variables
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commitdiff
2015-08-14
Clifford Wolf
Re-created command-reference-manual.tex, copied some...
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commitdiff
2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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commitdiff
2015-08-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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commitdiff
2015-08-12
Clifford Wolf
Adjust makefiles to work with out-of-tree builds
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commitdiff
2015-08-12
Clifford Wolf
Merge pull request #70 from gaomy3832/bugfix
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commitdiff
2015-08-11
Clifford Wolf
Fixed handling of [a-fxz?] in decimal constants
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commitdiff
2015-08-01
Clifford Wolf
Merge pull request #68 from zeldin/master
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commitdiff
2015-08-01
Marcus Comstedt
Add -noautowire option to verilog frontend
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commitdiff
2015-07-31
Clifford Wolf
Added WORDS parameter to $meminit
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commitdiff
2015-07-29
Clifford Wolf
Fixed nested mem2reg
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commitdiff
2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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commitdiff
2015-06-09
Clifford Wolf
Merge branch 'verilog-backend-memV2' of github.com...
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commitdiff
2015-06-08
Clifford Wolf
Fixed handling of parameters with reversed range
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commitdiff
2015-05-29
Clifford Wolf
Fixed signedness of genvar expressions
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commitdiff
2015-05-24
Clifford Wolf
Improvements in BLIF front-end
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commitdiff
2015-05-18
Clifford Wolf
bugfix in blif front-end
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commitdiff
2015-05-17
Clifford Wolf
Improved .latch support in BLIF front-end
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commitdiff
2015-05-17
Clifford Wolf
Added read_blif command
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commitdiff
2015-05-17
Clifford Wolf
Generalized blifparse API
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commitdiff
2015-05-17
Clifford Wolf
abc/blifparse files reorganization
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commitdiff
2015-05-17
Clifford Wolf
Verific build fixes
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commitdiff
2015-04-19
Clifford Wolf
Verilog front-end: define `BLACKBOX in -lib mode
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commitdiff
2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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commitdiff
2015-03-25
Clifford Wolf
Ignore celldefine directive in verilog front-end
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commitdiff
2015-03-01
Clifford Wolf
Const-fold parameter defs on-demand in AstNode::detectS...
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commitdiff
2015-02-26
Clifford Wolf
Added non-std verilog assume() statement
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commitdiff
2015-02-20
Clifford Wolf
Added deep recursion warning to AST simplify
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commitdiff
2015-02-20
Clifford Wolf
Parser support for complex delay expressions
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commitdiff
2015-02-19
Clifford Wolf
YosysJS stuff
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commitdiff
2015-02-18
Clifford Wolf
Convert floating point cell parameters to strings
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commitdiff
2015-02-14
Clifford Wolf
Various fixes for memories with offsets
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commitdiff
2015-02-14
Clifford Wolf
Added "read_verilog -nomeminit" and "nomeminit" attribute
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commitdiff
2015-02-14
Clifford Wolf
Creating $meminit cells in verilog front-end
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commitdiff
2015-02-14
Clifford Wolf
Fixed handling of "//" in filenames in verilog pre...
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commitdiff
2015-02-13
Clifford Wolf
Added AstNode::simplify() recursion counter
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commitdiff
2015-02-10
Clifford Wolf
Improved read_verilog support for empty behavioral...
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commitdiff
2015-02-07
Clifford Wolf
Ignore explicit assignments to constants in HDL code
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commitdiff
2015-02-07
Clifford Wolf
Fixed a bug with autowire bit size
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commitdiff
2015-01-24
Clifford Wolf
Added ENABLE_NDEBUG makefile options
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commitdiff
2015-01-15
Clifford Wolf
Ignoring more system task and functions
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commitdiff
2015-01-15
Clifford Wolf
Fixed handling of "input foo; reg [0:0] foo;"
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commitdiff
2015-01-15
Clifford Wolf
Consolidate "Blocking assignment to memory.." msgs...
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commitdiff
2015-01-08
Clifford Wolf
Merge pull request #46 from utzig/master
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