Fixed some typos
[yosys.git] / frontends /
2016-03-24 Clifford WolfDo not set "nosync" on task outputs, fixes #134
2016-03-21 Clifford WolfAdded support for $stop system task
2016-03-19 Clifford WolfAdded $display %m support, fixed mem leak in $display...
2016-03-18 Clifford WolfFixed localparam signdness, fixes #127
2016-03-18 Clifford WolfSet "nosync" attribute on internal task/function wires
2016-03-15 Clifford WolfFixed Verilog parser fix and more similar improvements
2016-03-15 Andrew BeckerUse left-recursive rule for cell_port_list in Verilog...
2016-03-11 Clifford WolfMerge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
2016-03-10 Clifford WolfFixed typos in verilog_defaults help message
2016-02-24 Clifford WolfFixed BLIF parser for empty port assignments
2016-02-13 Clifford WolfFixed some visual studio warnings
2016-02-13 Clifford WolfSupport for more Verific primitives (patch I got per...
2016-02-03 Clifford WolfBugfix in Verific front-end
2016-02-02 Clifford WolfUpdated verific build instructions
2016-02-02 Clifford WolfAdded addBufGate module method
2016-01-31 Clifford WolfMerge branch 'rtlil_remove2_speedup' of https://github...
2016-01-31 Rick Altherrgenrtlil: avoid converting SigSpec to set<SigBit> when...
2015-12-20 Clifford WolfVarious improvements in BLIF front-end
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-11-29 Clifford WolfFixed oom bug in ilang parser
2015-11-27 Clifford WolfFixed performance bug in ilang parser
2015-11-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-11-24 Clifford WolfAdded PRIM_DLATCHRS support to verific front-end
2015-11-23 Clifford WolfFixed handling of re-declarations of wires in tasks...
2015-11-16 Clifford WolfFixed performance bug in Verific importer
2015-11-12 Clifford WolfChanges for Verific 3.16_484_32_151112
2015-11-12 Clifford WolfMore bugfixes in handling of parameters in tasks and...
2015-11-11 Clifford WolfFixed handling of parameters and localparams in functions
2015-10-25 Clifford WolfImport more std:: stuff into Yosys namespace
2015-10-15 Clifford WolfFixed bug in verilog parser
2015-10-13 Clifford WolfSystemVerilog also has assume(), added implicit -D...
2015-10-07 Clifford WolfAdded support for "parameter" and "localparam" in globa...
2015-10-01 Clifford WolfFixed complexity of assigning to vectors in constant...
2015-09-30 Clifford WolfFixed detection of unconditional $readmem[hb]
2015-09-25 Clifford WolfBugfixes in $readmem[hb]
2015-09-25 Clifford WolfFixed segfault in AstNode::asReal
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-09-24 Clifford WolfFixed AstNode::mkconst_bits() segfault on zero-sized...
2015-09-23 Clifford WolfAdded read_verilog -nodpi
2015-09-23 Clifford WolfBugfix in handling of multi-dimensional memories
2015-09-23 Clifford WolfWarning for $display/$write outside initial block
2015-09-23 Clifford WolfFixed support for $write system task
2015-09-22 Clifford WolfFixed detection of "task foo(bar);" syntax error
2015-09-22 Clifford WolfFixed multi-level prefix resolving
2015-09-22 Clifford WolfFixed segfault on invalid verilog constant 1'b_
2015-09-19 Andrew ZonenbergImprovements to $display system task
2015-09-18 Clifford WolfMerge branch 'feat-finish-disp'
2015-09-18 Clifford WolfAdded AST_INITIAL checks for $finish and $display
2015-09-18 Andrew ZonenbergInitial implementation of $display()
2015-09-18 Andrew ZonenbergInitial implementation of $finish()
2015-09-01 Clifford Wolfgcc-4.6 build fixes
2015-08-22 Clifford WolfFixed handling of memory read without address
2015-08-17 Clifford WolfSmall corrections to const2ast warning messages
2015-08-17 Florian ZeitzCheck base-n literals only contain valid digits
2015-08-17 Florian ZeitzWarn on literals exceeding the specified bit width
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-08-14 Larry DoolittleKeep gcc from complaining about uninitialized variables
2015-08-14 Clifford WolfRe-created command-reference-manual.tex, copied some...
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-12 Clifford WolfAdjust makefiles to work with out-of-tree builds
2015-08-12 Clifford WolfMerge pull request #70 from gaomy3832/bugfix
2015-08-11 Clifford WolfFixed handling of [a-fxz?] in decimal constants
2015-08-01 Clifford WolfMerge pull request #68 from zeldin/master
2015-08-01 Marcus ComstedtAdd -noautowire option to verilog frontend
2015-07-31 Clifford WolfAdded WORDS parameter to $meminit
2015-07-29 Clifford WolfFixed nested mem2reg
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-06-09 Clifford WolfMerge branch 'verilog-backend-memV2' of github.com...
2015-06-08 Clifford WolfFixed handling of parameters with reversed range
2015-05-29 Clifford WolfFixed signedness of genvar expressions
2015-05-24 Clifford WolfImprovements in BLIF front-end
2015-05-18 Clifford Wolfbugfix in blif front-end
2015-05-17 Clifford WolfImproved .latch support in BLIF front-end
2015-05-17 Clifford WolfAdded read_blif command
2015-05-17 Clifford WolfGeneralized blifparse API
2015-05-17 Clifford Wolfabc/blifparse files reorganization
2015-05-17 Clifford WolfVerific build fixes
2015-04-19 Clifford WolfVerilog front-end: define `BLACKBOX in -lib mode
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-03-25 Clifford WolfIgnore celldefine directive in verilog front-end
2015-03-01 Clifford WolfConst-fold parameter defs on-demand in AstNode::detectS...
2015-02-26 Clifford WolfAdded non-std verilog assume() statement
2015-02-20 Clifford WolfAdded deep recursion warning to AST simplify
2015-02-20 Clifford WolfParser support for complex delay expressions
2015-02-19 Clifford WolfYosysJS stuff
2015-02-18 Clifford WolfConvert floating point cell parameters to strings
2015-02-14 Clifford WolfVarious fixes for memories with offsets
2015-02-14 Clifford WolfAdded "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 Clifford WolfCreating $meminit cells in verilog front-end
2015-02-14 Clifford WolfFixed handling of "//" in filenames in verilog pre...
2015-02-13 Clifford WolfAdded AstNode::simplify() recursion counter
2015-02-10 Clifford WolfImproved read_verilog support for empty behavioral...
2015-02-07 Clifford WolfIgnore explicit assignments to constants in HDL code
2015-02-07 Clifford WolfFixed a bug with autowire bit size
2015-01-24 Clifford WolfAdded ENABLE_NDEBUG makefile options
2015-01-15 Clifford WolfIgnoring more system task and functions
2015-01-15 Clifford WolfFixed handling of "input foo; reg [0:0] foo;"
2015-01-15 Clifford WolfConsolidate "Blocking assignment to memory.." msgs...
2015-01-08 Clifford WolfMerge pull request #46 from utzig/master
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