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write_verilog: write $tribuf cell as ternary.
[yosys.git] / frontends /
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs tree | commitdiff
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire tree | commitdiff
2019-01-05 Clifford WolfBugfix in Verilog string handling tree | commitdiff
2019-01-04 Clifford WolfMerge pull request #777 from mmicko/achronix_cell_sim_fix tree | commitdiff
2019-01-04 Clifford WolfRemove -m32 Verific eval lib build instructions tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init tree | commitdiff
2019-01-02 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut tree | commitdiff
2019-01-02 Clifford WolfImprove VerificImporter support for writes to asymmetri... tree | commitdiff
2019-01-02 Clifford WolfFix VerificImporter asymmetric memories error message tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos tree | commitdiff
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste... tree | commitdiff
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches tree | commitdiff
2018-12-23 Clifford WolfMerge pull request #761 from whitequark/proc_clean_partial tree | commitdiff
2018-12-23 Clifford WolfAdd "read_ilang -[no]overwrite" tree | commitdiff
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem tree | commitdiff
2018-12-19 Clifford WolfMerge pull request #752 from Icenowy/anlogic-lut-cost tree | commitdiff
2018-12-19 Clifford WolfMerge pull request #753 from Icenowy/anlogic-makefile-fix tree | commitdiff
2018-12-19 Clifford WolfMerge pull request #749 from Icenowy/anlogic-dram-fix tree | commitdiff
2018-12-18 Clifford WolfMerge pull request #748 from makaimann/add-btor-ops tree | commitdiff
2018-12-18 Clifford WolfFix segfault in AST simplify tree | commitdiff
2018-12-18 Clifford WolfImprove src tagging (using names and attrs) of cells... tree | commitdiff
2018-12-17 Clifford WolfMerge pull request #746 from Icenowy/anlogic-dram tree | commitdiff
2018-12-17 Clifford WolfMerge pull request #742 from whitequark/changelog tree | commitdiff
2018-12-17 Clifford WolfMerge pull request #741 from whitequark/ilang_slice_sigspec tree | commitdiff
2018-12-16 whitequarkread_ilang: allow slicing sigspecs. tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737 tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #723 from whitequark/synth_ice40_map... tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #722 from whitequark/rename_src tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #720 from whitequark/master tree | commitdiff
2018-12-14 Sylvain Munautverilog_parser: Properly handle recursion when processi... tree | commitdiff
2018-12-06 Clifford WolfVerific updates tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708 tree | commitdiff
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master tree | commitdiff
2018-11-24 Sylvain MunautMake return value of $clog2 signed tree | commitdiff
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb tree | commitdiff
2018-11-09 Clifford WolfSet Verific flag vhdl_support_variable_slice=1 tree | commitdiff
2018-11-05 Clifford WolfAllow square brackets in liberty identifiers tree | commitdiff
2018-11-04 Clifford WolfAdd warning for SV "restrict" without "property" tree | commitdiff
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space... tree | commitdiff
2018-11-04 Clifford WolfMerge pull request #687 from trcwm/master tree | commitdiff
2018-11-04 Clifford WolfMerge pull request #688 from ZipCPU/rosenfell tree | commitdiff
2018-11-03 ZipCPUMake and dependent upon LSB only tree | commitdiff
2018-11-01 Clifford WolfDo not generate "reg assigned in a continuous assignmen... tree | commitdiff
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master tree | commitdiff
2018-10-25 Clifford WolfFix minor typo in error message tree | commitdiff
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error tree | commitdiff
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the... tree | commitdiff
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp tree | commitdiff
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning tree | commitdiff
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface... tree | commitdiff
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments tree | commitdiff
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the... tree | commitdiff
2018-10-20 Ruben UndheimFixed memory leak tree | commitdiff
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram tree | commitdiff
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces tree | commitdiff
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr tree | commitdiff
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect tree | commitdiff
2018-10-17 Clifford WolfMinor code cleanups in liberty front-end tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #660 from tklam/parse-liberty-detect... tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #658 from daveshah1/ecp5_bram tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #641 from tklam/master tree | commitdiff
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error tree | commitdiff
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc' tree | commitdiff
2018-10-16 argamaignore protect endprotect tree | commitdiff
2018-10-13 Ruben UndheimHandle FIXME for modport members without type directly... tree | commitdiff
2018-10-13 Ruben UndheimDocumentation improvements etc. tree | commitdiff
2018-10-13 argamadetect ff/latch before processing other nodes tree | commitdiff
2018-10-13 tklamMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2018-10-12 Ruben UndheimFix build error with clang tree | commitdiff
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces tree | commitdiff
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces tree | commitdiff
2018-10-07 Clifford WolfImprove Verific importer blackbox handling tree | commitdiff
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix tree | commitdiff
2018-10-05 Clifford WolfMerge pull request #654 from mithro/patch-1 tree | commitdiff
2018-10-05 Clifford WolfFix compiler warning in verific.cc tree | commitdiff
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix tree | commitdiff
2018-10-02 Clifford WolfMerge pull request #646 from tomverbeure/issue594 tree | commitdiff
2018-10-02 Tom VerbeureFix for issue 594. tree | commitdiff
2018-10-01 Dan GisselquistAdd read_verilog $changed support tree | commitdiff
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master tree | commitdiff
2018-09-30 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys tree | commitdiff
2018-09-30 Clifford WolfFix handling of $past 2nd argument in read_verilog tree | commitdiff
2018-09-28 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys tree | commitdiff
2018-09-24 Udi FinkelsteinFixed issue #630 by fixing a minor typo in the previous... tree | commitdiff
2018-09-24 Clifford WolfAdd "read_verilog -noassert -noassume -assert-assumes" tree | commitdiff
2018-09-23 Clifford WolfAdded support for ommited "parameter" in Verilog-2001... tree | commitdiff
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error tree | commitdiff
2018-09-17 Udi FinkelsteinFixed remaining cases where we check fo wire reg/wire... tree | commitdiff
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master tree | commitdiff
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