Initial support for Anlogic FPGA
[yosys.git] / frontends /
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-09 Clifford WolfSet Verific flag vhdl_support_variable_slice=1
2018-11-05 Clifford WolfAllow square brackets in liberty identifiers
2018-11-04 Clifford WolfAdd warning for SV "restrict" without "property"
2018-11-04 Clifford WolfVarious indenting fixes in AST front-end (mostly space...
2018-11-04 Clifford WolfMerge pull request #687 from trcwm/master
2018-11-04 Clifford WolfMerge pull request #688 from ZipCPU/rosenfell
2018-11-03 ZipCPUMake and dependent upon LSB only
2018-11-01 Clifford WolfDo not generate "reg assigned in a continuous assignmen...
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master
2018-10-25 Clifford WolfFix minor typo in error message
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the...
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface...
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the...
2018-10-20 Ruben UndheimFixed memory leak
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect
2018-10-17 Clifford WolfMinor code cleanups in liberty front-end
2018-10-17 Clifford WolfMerge pull request #660 from tklam/parse-liberty-detect...
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
2018-10-17 Clifford WolfMerge pull request #658 from daveshah1/ecp5_bram
2018-10-17 Clifford WolfMerge pull request #641 from tklam/master
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-16 argamaignore protect endprotect
2018-10-13 Ruben UndheimHandle FIXME for modport members without type directly...
2018-10-13 Ruben UndheimDocumentation improvements etc.
2018-10-13 argamadetect ff/latch before processing other nodes
2018-10-13 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-12 Ruben UndheimFix build error with clang
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-10-07 Clifford WolfImprove Verific importer blackbox handling
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix
2018-10-05 Clifford WolfMerge pull request #654 from mithro/patch-1
2018-10-05 Clifford WolfFix compiler warning in verific.cc
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix
2018-10-02 Clifford WolfMerge pull request #646 from tomverbeure/issue594
2018-10-02 Tom VerbeureFix for issue 594.
2018-10-01 Dan GisselquistAdd read_verilog $changed support
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master
2018-09-30 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-30 Clifford WolfFix handling of $past 2nd argument in read_verilog
2018-09-28 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-24 Udi FinkelsteinFixed issue #630 by fixing a minor typo in the previous...
2018-09-24 Clifford WolfAdd "read_verilog -noassert -noassume -assert-assumes"
2018-09-23 Clifford WolfAdded support for ommited "parameter" in Verilog-2001...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-09-17 Udi FinkelsteinFixed remaining cases where we check fo wire reg/wire...
2018-09-14 Clifford WolfMerge pull request #625 from aman-goel/master
2018-09-04 Clifford WolfAdd "verific -L <int>" option
2018-08-27 Jim LawsonMerge branch 'master' into firrtl+modules+shiftfixes
2018-08-27 Jim LawsonMerge pull request #3 from YosysHQ/master
2018-08-27 Clifford WolfAdd "make coverage"
2018-08-23 Clifford WolfMerge pull request #610 from udif/udif_specify_round2
2018-08-23 Clifford WolfMerge pull request #614 from udif/pr_disable_dump_ptr
2018-08-23 Udi FinkelsteinAdded -no_dump_ptr flag for AST dump options in 'read_v...
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-22 Clifford WolfAdd "verific -work" help message
2018-08-22 Clifford WolfAdd Verific -work parameter
2018-08-20 Udi FinkelsteinFixed all known specify/endspecify issues, without...
2018-08-19 Udi FinkelsteinYosys can now parse https://github.com/verilog-to-routi...
2018-08-19 Clifford WolfMerge pull request #606 from cr1901/show-win
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-16 Clifford WolfAdd "verific -set-<severity> <msg_id>.."
2018-08-16 Clifford WolfVerific workaround for VIPER ticket 13851
2018-08-15 Udi FinkelsteinA few minor enhancements to specify block parsing.
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file...
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-08-14 Clifford WolfMerge pull request #602 from litghost/add_eblif_extension
2018-08-08 Clifford WolfFixed use of char array for string in blifparse error...
2018-08-08 Clifford WolfMerge pull request #596 from litghost/extend_blif_parser
2018-08-08 litghostReport error reason on same line as syntax error.
2018-08-03 litghostUse log_warning which does not immediately terminate.
2018-08-02 litghostAdd BLIF parsing support for .conn and .cname
2018-07-22 Clifford WolfVerific: Produce errors for instantiating unknown module
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-07-21 Henner ZellerFix remaining log_file_error(); emit dependent file...
2018-07-20 Clifford WolfMerge pull request #586 from hzeller/more-sourcepos...
2018-07-20 Henner ZellerConvert more log_error() to log_file_error() where...
2018-07-20 Clifford WolfMerge pull request #585 from hzeller/use-file-warning...
2018-07-20 Henner ZellerUse log_file_warning(), log_file_error() functions.
2018-07-20 Clifford WolfMerge pull request #584 from hzeller/provide-source...
2018-07-19 Henner ZellerProvide source-location logging.
2018-07-18 Aman GoelMerge pull request #2 from YosysHQ/master
2018-07-17 Clifford WolfFix handling of eventually properties in verific importer
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