2017-12-10 |
Clifford Wolf | Add support for Verific PRIM_SVA_NOT properties |
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2017-12-09 |
Clifford Wolf | Add Verific OPER_SVA_STABLE support |
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2017-12-09 |
Clifford Wolf | Refactoring Verific SVA rewriter |
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2017-12-02 |
Clifford Wolf | Fix error handling for nested always/initial |
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2017-11-28 |
Clifford Wolf | Merge pull request #462 from daveshah1/up5k |
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2017-11-24 |
Clifford Wolf | Merge pull request #446 from mithro/travis-rework |
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2017-11-23 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2017-11-23 |
Clifford Wolf | Add Verilog "automatic" keyword (ignored in synthesis) |
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2017-11-18 |
Clifford Wolf | Merge pull request #455 from daveshah1/up5k |
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2017-11-18 |
Clifford Wolf | Accept real-valued delay values |
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2017-11-18 |
Clifford Wolf | Merge pull request #452 from cr1901/master |
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2017-11-14 |
William D. Jones | Accommodate Windows-style paths during include-file... |
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2017-11-09 |
dh73 | Merge https://github.com/cliffordwolf/yosys |
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2017-10-25 |
Clifford Wolf | Remove vhdl2verilog |
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2017-10-20 |
Clifford Wolf | Remove all PSL support code from verific.cc |
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2017-10-13 |
Clifford Wolf | Add "verific -vlog-libdir" |
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2017-10-13 |
Clifford Wolf | Add "verific -vlog-incdir" and "verific -vlog-define" |
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2017-10-13 |
Clifford Wolf | Update Verific README |
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2017-10-12 |
Clifford Wolf | Merge pull request #434 from Kmanfi/vector_fix |
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2017-10-12 |
Clifford Wolf | Add Verific fairness/liveness support |
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2017-10-10 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2017-10-10 |
Clifford Wolf | Start work on pre-processor for Verific SVA properties |
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2017-10-10 |
Clifford Wolf | Remove some dead code |
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2017-10-10 |
Clifford Wolf | Allow $past, $stable, $rose, $fell in $global_clock... |
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2017-10-05 |
Clifford Wolf | Improve handling of Verific errors |
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2017-10-04 |
Clifford Wolf | Improve Verific error handling, check VHDL static asserts |
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2017-10-04 |
Clifford Wolf | Fix nasty bug in Verific bindings |
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2017-10-03 |
Clifford Wolf | Merge branch 'pr_ast_const_funcs' of https://github... |
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2017-10-03 |
Clifford Wolf | Merge branch 'fix_shift_reduce_conflict' of https:... |
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2017-09-30 |
Udi Finkelstein | Turned a few member functions into const, esp. dumpAst... |
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2017-09-30 |
Udi Finkelstein | Resolved classical Bison IF/THEN/ELSE shift/reduce... |
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2017-09-29 |
Clifford Wolf | Allow $size and $bits in verilog mode, actually check... |
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2017-09-29 |
Clifford Wolf | Merge pull request #425 from udif/udif_dollar_bits |
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2017-09-27 |
Clifford Wolf | Increase maximum LUT size in blifparse to 12 bits |
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2017-09-26 |
Udi Finkelstein | $size() now works correctly for all cases! |
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2017-09-26 |
Udi Finkelstein | $size() seems to work now with or without the optional... |
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2017-09-26 |
Clifford Wolf | Parse reals as string in JSON front-end |
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2017-09-26 |
Clifford Wolf | Merge branch 'vlogpp-inc-fixes' |
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2017-09-26 |
Clifford Wolf | Minor coding style fix |
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2017-09-26 |
Clifford Wolf | Merge branch 'master' of https://github.com/combinatory... |
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2017-09-26 |
Udi Finkelstein | enable $bits() and $size() functions only when the... |
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2017-09-26 |
Udi Finkelstein | Added $bits() for memories as well. |
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2017-09-26 |
Udi Finkelstein | $size() now works with memories as well! |
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2017-09-26 |
Udi Finkelstein | Add $size() function. At the moment it works only on... |
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2017-09-25 |
Clifford Wolf | Fix ignoring of simulation timings so that invalid... |
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2017-09-21 |
combinatorylogic | Adding support for string macros and macros with argume... |
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2017-08-15 |
Clifford Wolf | Merge branch 'rmports' of https://github.com/azonenberg... |
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2017-08-14 |
Clifford Wolf | Merge pull request #381 from azonenberg/countfix |
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2017-08-14 |
Clifford Wolf | Merge pull request #383 from azonenberg/abcfnames |
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2017-08-14 |
Clifford Wolf | Merge pull request #382 from azonenberg/jsoniofix |
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2017-08-14 |
Robert Ou | json: Parse inout correctly rather than as an output |
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2017-07-28 |
Clifford Wolf | Add merging of "past FFs" to verific importer |
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2017-07-28 |
Clifford Wolf | Add minimal support for PSL in VHDL via Verific |
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2017-07-28 |
Clifford Wolf | Improve Verific HDL language options |
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2017-07-28 |
Clifford Wolf | Fix handling of non-user-declared Verific netbus |
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2017-07-27 |
Clifford Wolf | Improve Verific SVA importer |
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2017-07-27 |
Clifford Wolf | Add log_warning_noprefix() API, Use for Verific warning... |
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2017-07-27 |
Clifford Wolf | Add "verific -import -n" and "verific -import -nosva" |
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2017-07-27 |
Clifford Wolf | Improve Verific SVA import: negedge and $past |
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2017-07-27 |
Clifford Wolf | Improve Verific SVA importer |
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2017-07-26 |
Clifford Wolf | Improve Verific bindings (mostly related to SVA) |
tree | commitdiff |
2017-07-25 |
Clifford Wolf | Improve "help verific" message |
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2017-07-25 |
Clifford Wolf | Add "verific -extnets" |
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2017-07-25 |
Clifford Wolf | Improve "verific -all" handling |
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2017-07-24 |
Clifford Wolf | Add "verific -import -d <dump_file" |
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2017-07-24 |
Clifford Wolf | Add "verific -import -flatten" and "verific -import -v" |
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2017-07-22 |
Clifford Wolf | Add "verific -import -k" |
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2017-07-22 |
Clifford Wolf | Improve docs for verific bindings, add simply sby example |
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2017-07-21 |
Clifford Wolf | Fix "read_blif -wideports" handling of cells with wide... |
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2017-07-21 |
Clifford Wolf | Add a paragraph about pre-defined macros to read_verilo... |
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2017-07-10 |
Clifford Wolf | Add attributes and parameter support to JSON front-end |
tree | commitdiff |
2017-07-08 |
Clifford Wolf | Add JSON front-end |
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2017-07-04 |
Clifford Wolf | Add Verific Release information to log |
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2017-06-07 |
Clifford Wolf | Fix generation of vlogtb output in yosys-smtbmc for... |
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2017-06-01 |
Clifford Wolf | Fix handling of Verilog ~& and ~| operators |
tree | commitdiff |
2017-04-30 |
Clifford Wolf | Add support for localparam in module header |
tree | commitdiff |
2017-04-26 |
Clifford Wolf | Add support for `resetall compiler directive |
tree | commitdiff |
2017-03-14 |
Clifford Wolf | Fix verilog pre-processor for multi-level relative... |
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2017-03-01 |
Clifford Wolf | Allow $anyconst, etc. in non-formal SV mode |
tree | commitdiff |
2017-02-25 |
Clifford Wolf | Merge branch 'master' of https://github.com/klammerj... |
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2017-02-25 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2017-02-25 |
Clifford Wolf | Add $live and $fair cell types, add support for s_event... |
tree | commitdiff |
2017-02-24 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-02-23 |
Clifford Wolf | Add support for SystemVerilog unique, unique0, and... |
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2017-02-23 |
Clifford Wolf | Preserve string parameters |
tree | commitdiff |
2017-02-23 |
Clifford Wolf | Added SystemVerilog support for ++ and -- |
tree | commitdiff |
2017-02-14 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-02-14 |
Clifford Wolf | Fix incorrect "incompatible re-declaration of wire... |
tree | commitdiff |
2017-02-11 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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2017-02-11 |
Clifford Wolf | Add support for verific mem initialization |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Fix another stupid bug in the same line |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Add verific support for initialized variables |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Improve handling of Verific warnings and error messages |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Fix extremely stupid typo |
tree | commitdiff |
2017-02-11 |
Clifford Wolf | Merge branch 'master' of https://github.com/stv0g/yosys... |
tree | commitdiff |
2017-02-09 |
Clifford Wolf | Add checker support to verilog front-end |
tree | commitdiff |
2017-02-09 |
Clifford Wolf | Add "rand" and "rand const" verific support |
tree | commitdiff |
2017-02-09 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
tree | commitdiff |
2017-02-08 |
Clifford Wolf | Add SV "rand" and "const rand" support |
tree | commitdiff |
2017-02-08 |
Clifford Wolf | Add PSL parser mode to verific front-end |
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