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Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys
[yosys.git]
/
frontends
/
2017-10-03
Clifford Wolf
Merge branch 'fix_shift_reduce_conflict' of https:...
tree
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commitdiff
2017-09-30
Udi Finkelstein
Resolved classical Bison IF/THEN/ELSE shift/reduce...
tree
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commitdiff
2017-09-29
Clifford Wolf
Allow $size and $bits in verilog mode, actually check...
tree
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commitdiff
2017-09-29
Clifford Wolf
Merge pull request #425 from udif/udif_dollar_bits
tree
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commitdiff
2017-09-27
Clifford Wolf
Increase maximum LUT size in blifparse to 12 bits
tree
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commitdiff
2017-09-26
Udi Finkelstein
$size() now works correctly for all cases!
tree
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commitdiff
2017-09-26
Udi Finkelstein
$size() seems to work now with or without the optional...
tree
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commitdiff
2017-09-26
Clifford Wolf
Parse reals as string in JSON front-end
tree
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commitdiff
2017-09-26
Clifford Wolf
Merge branch 'vlogpp-inc-fixes'
tree
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commitdiff
2017-09-26
Clifford Wolf
Minor coding style fix
tree
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commitdiff
2017-09-26
Clifford Wolf
Merge branch 'master' of https://github.com/combinatory...
tree
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commitdiff
2017-09-26
Udi Finkelstein
enable $bits() and $size() functions only when the...
tree
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commitdiff
2017-09-26
Udi Finkelstein
Added $bits() for memories as well.
tree
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commitdiff
2017-09-26
Udi Finkelstein
$size() now works with memories as well!
tree
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commitdiff
2017-09-26
Udi Finkelstein
Add $size() function. At the moment it works only on...
tree
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commitdiff
2017-09-25
Clifford Wolf
Fix ignoring of simulation timings so that invalid...
tree
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commitdiff
2017-09-21
combinatorylogic
Adding support for string macros and macros with argume...
tree
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commitdiff
2017-08-15
Clifford Wolf
Merge branch 'rmports' of https://github.com/azonenberg...
tree
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commitdiff
2017-08-14
Clifford Wolf
Merge pull request #381 from azonenberg/countfix
tree
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commitdiff
2017-08-14
Clifford Wolf
Merge pull request #383 from azonenberg/abcfnames
tree
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commitdiff
2017-08-14
Clifford Wolf
Merge pull request #382 from azonenberg/jsoniofix
tree
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commitdiff
2017-08-14
Robert Ou
json: Parse inout correctly rather than as an output
tree
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commitdiff
2017-07-28
Clifford Wolf
Add merging of "past FFs" to verific importer
tree
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commitdiff
2017-07-28
Clifford Wolf
Add minimal support for PSL in VHDL via Verific
tree
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commitdiff
2017-07-28
Clifford Wolf
Improve Verific HDL language options
tree
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commitdiff
2017-07-28
Clifford Wolf
Fix handling of non-user-declared Verific netbus
tree
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commitdiff
2017-07-27
Clifford Wolf
Improve Verific SVA importer
tree
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commitdiff
2017-07-27
Clifford Wolf
Add log_warning_noprefix() API, Use for Verific warning...
tree
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commitdiff
2017-07-27
Clifford Wolf
Add "verific -import -n" and "verific -import -nosva"
tree
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commitdiff
2017-07-27
Clifford Wolf
Improve Verific SVA import: negedge and $past
tree
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commitdiff
2017-07-27
Clifford Wolf
Improve Verific SVA importer
tree
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commitdiff
2017-07-26
Clifford Wolf
Improve Verific bindings (mostly related to SVA)
tree
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commitdiff
2017-07-25
Clifford Wolf
Improve "help verific" message
tree
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commitdiff
2017-07-25
Clifford Wolf
Add "verific -extnets"
tree
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commitdiff
2017-07-25
Clifford Wolf
Improve "verific -all" handling
tree
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commitdiff
2017-07-24
Clifford Wolf
Add "verific -import -d <dump_file"
tree
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commitdiff
2017-07-24
Clifford Wolf
Add "verific -import -flatten" and "verific -import -v"
tree
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commitdiff
2017-07-22
Clifford Wolf
Add "verific -import -k"
tree
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commitdiff
2017-07-22
Clifford Wolf
Improve docs for verific bindings, add simply sby example
tree
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commitdiff
2017-07-21
Clifford Wolf
Fix "read_blif -wideports" handling of cells with wide...
tree
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commitdiff
2017-07-21
Clifford Wolf
Add a paragraph about pre-defined macros to read_verilo...
tree
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commitdiff
2017-07-10
Clifford Wolf
Add attributes and parameter support to JSON front-end
tree
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commitdiff
2017-07-08
Clifford Wolf
Add JSON front-end
tree
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commitdiff
2017-07-04
Clifford Wolf
Add Verific Release information to log
tree
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commitdiff
2017-06-07
Clifford Wolf
Fix generation of vlogtb output in yosys-smtbmc for...
tree
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commitdiff
2017-06-01
Clifford Wolf
Fix handling of Verilog ~& and ~| operators
tree
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commitdiff
2017-04-30
Clifford Wolf
Add support for localparam in module header
tree
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commitdiff
2017-04-26
Clifford Wolf
Add support for `resetall compiler directive
tree
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commitdiff
2017-03-14
Clifford Wolf
Fix verilog pre-processor for multi-level relative...
tree
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commitdiff
2017-03-01
Clifford Wolf
Allow $anyconst, etc. in non-formal SV mode
tree
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commitdiff
2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
tree
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commitdiff
2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
tree
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commitdiff
2017-02-24
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-02-23
Clifford Wolf
Add support for SystemVerilog unique, unique0, and...
tree
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commitdiff
2017-02-23
Clifford Wolf
Preserve string parameters
tree
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commitdiff
2017-02-23
Clifford Wolf
Added SystemVerilog support for ++ and --
tree
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commitdiff
2017-02-14
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-02-14
Clifford Wolf
Fix incorrect "incompatible re-declaration of wire...
tree
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commitdiff
2017-02-11
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-02-11
Clifford Wolf
Add support for verific mem initialization
tree
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commitdiff
2017-02-11
Clifford Wolf
Fix another stupid bug in the same line
tree
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commitdiff
2017-02-11
Clifford Wolf
Add verific support for initialized variables
tree
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commitdiff
2017-02-11
Clifford Wolf
Improve handling of Verific warnings and error messages
tree
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commitdiff
2017-02-11
Clifford Wolf
Fix extremely stupid typo
tree
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commitdiff
2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
tree
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commitdiff
2017-02-09
Clifford Wolf
Add checker support to verilog front-end
tree
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commitdiff
2017-02-09
Clifford Wolf
Add "rand" and "rand const" verific support
tree
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commitdiff
2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-02-08
Clifford Wolf
Add SV "rand" and "const rand" support
tree
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commitdiff
2017-02-08
Clifford Wolf
Add PSL parser mode to verific front-end
tree
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commitdiff
2017-02-06
Clifford Wolf
Add "read_blif -wideports"
tree
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commitdiff
2017-02-04
Clifford Wolf
Further improve cover() support
tree
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commitdiff
2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
tree
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commitdiff
2017-02-04
Clifford Wolf
Add assert/assume support to verific front-end
tree
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commitdiff
2017-01-31
Clifford Wolf
Merge branch 'opt_compare_pr' of https://github.com...
tree
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commitdiff
2017-01-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-01-17
Clifford Wolf
Add "enum" and "typedef" lexer support
tree
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commitdiff
2017-01-15
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-01-15
Clifford Wolf
Fix bug in AstNode::mem2reg_as_needed_pass2()
tree
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commitdiff
2017-01-05
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-01-05
Clifford Wolf
Fixed handling of local memories in functions
tree
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commitdiff
2017-01-04
Clifford Wolf
Added handling of local memories and error for local...
tree
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commitdiff
2017-01-03
Clifford Wolf
Added Verilog $rtoi and $itor support
tree
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commitdiff
2016-12-23
Andrew Zonenberg
Merge pull request #1 from azonenberg-hk/master
tree
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commitdiff
2016-12-17
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2016-12-15
Clifford Wolf
Added "verilog_defines" command
tree
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commitdiff
2016-11-28
Clifford Wolf
Added support for macros as include file names
tree
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commitdiff
2016-11-28
Clifford Wolf
Bugfix in "read_verilog -D NAME=VAL" handling
tree
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commitdiff
2016-11-15
Clifford Wolf
Added support for hierarchical defparams
tree
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commitdiff
2016-11-15
Clifford Wolf
Remember global declarations and defines accross read_v...
tree
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commitdiff
2016-11-04
Clifford Wolf
Fixed anonymous genblock object names
tree
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commitdiff
2016-11-01
Clifford Wolf
Some fixes in handling of signed arrays
tree
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commitdiff
2016-10-22
Clifford Wolf
Added avail params to ilang format, check module params...
tree
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commitdiff
2016-10-19
Clifford Wolf
No limit for length of lines in BLIF front-end
tree
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commitdiff
2016-10-14
Clifford Wolf
Added $anyseq cell type
tree
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commitdiff
2016-10-14
Clifford Wolf
Added $global_clock verilog syntax support for creating...
tree
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commitdiff
2016-10-11
Clifford Wolf
Added $ff and $_FF_ cell types
tree
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commitdiff
2016-09-23
Clifford Wolf
Added liberty parser support for types within cell...
tree
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commitdiff
2016-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/brouhaha...
tree
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commitdiff
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