Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys
[yosys.git] / frontends /
2017-10-03 Clifford WolfMerge branch 'fix_shift_reduce_conflict' of https:...
2017-09-30 Udi FinkelsteinResolved classical Bison IF/THEN/ELSE shift/reduce...
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check...
2017-09-29 Clifford WolfMerge pull request #425 from udif/udif_dollar_bits
2017-09-27 Clifford WolfIncrease maximum LUT size in blifparse to 12 bits
2017-09-26 Udi Finkelstein$size() now works correctly for all cases!
2017-09-26 Udi Finkelstein$size() seems to work now with or without the optional...
2017-09-26 Clifford WolfParse reals as string in JSON front-end
2017-09-26 Clifford WolfMerge branch 'vlogpp-inc-fixes'
2017-09-26 Clifford WolfMinor coding style fix
2017-09-26 Clifford WolfMerge branch 'master' of https://github.com/combinatory...
2017-09-26 Udi Finkelsteinenable $bits() and $size() functions only when the...
2017-09-26 Udi FinkelsteinAdded $bits() for memories as well.
2017-09-26 Udi Finkelstein$size() now works with memories as well!
2017-09-26 Udi FinkelsteinAdd $size() function. At the moment it works only on...
2017-09-25 Clifford WolfFix ignoring of simulation timings so that invalid...
2017-09-21 combinatorylogicAdding support for string macros and macros with argume...
2017-08-15 Clifford WolfMerge branch 'rmports' of https://github.com/azonenberg...
2017-08-14 Clifford WolfMerge pull request #381 from azonenberg/countfix
2017-08-14 Clifford WolfMerge pull request #383 from azonenberg/abcfnames
2017-08-14 Clifford WolfMerge pull request #382 from azonenberg/jsoniofix
2017-08-14 Robert Oujson: Parse inout correctly rather than as an output
2017-07-28 Clifford WolfAdd merging of "past FFs" to verific importer
2017-07-28 Clifford WolfAdd minimal support for PSL in VHDL via Verific
2017-07-28 Clifford WolfImprove Verific HDL language options
2017-07-28 Clifford WolfFix handling of non-user-declared Verific netbus
2017-07-27 Clifford WolfImprove Verific SVA importer
2017-07-27 Clifford WolfAdd log_warning_noprefix() API, Use for Verific warning...
2017-07-27 Clifford WolfAdd "verific -import -n" and "verific -import -nosva"
2017-07-27 Clifford WolfImprove Verific SVA import: negedge and $past
2017-07-27 Clifford WolfImprove Verific SVA importer
2017-07-26 Clifford WolfImprove Verific bindings (mostly related to SVA)
2017-07-25 Clifford WolfImprove "help verific" message
2017-07-25 Clifford WolfAdd "verific -extnets"
2017-07-25 Clifford WolfImprove "verific -all" handling
2017-07-24 Clifford WolfAdd "verific -import -d <dump_file"
2017-07-24 Clifford WolfAdd "verific -import -flatten" and "verific -import -v"
2017-07-22 Clifford WolfAdd "verific -import -k"
2017-07-22 Clifford WolfImprove docs for verific bindings, add simply sby example
2017-07-21 Clifford WolfFix "read_blif -wideports" handling of cells with wide...
2017-07-21 Clifford WolfAdd a paragraph about pre-defined macros to read_verilo...
2017-07-10 Clifford WolfAdd attributes and parameter support to JSON front-end
2017-07-08 Clifford WolfAdd JSON front-end
2017-07-04 Clifford WolfAdd Verific Release information to log
2017-06-07 Clifford WolfFix generation of vlogtb output in yosys-smtbmc for...
2017-06-01 Clifford WolfFix handling of Verilog ~& and ~| operators
2017-04-30 Clifford WolfAdd support for localparam in module header
2017-04-26 Clifford WolfAdd support for `resetall compiler directive
2017-03-14 Clifford WolfFix verilog pre-processor for multi-level relative...
2017-03-01 Clifford WolfAllow $anyconst, etc. in non-formal SV mode
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-23 Clifford WolfAdd support for SystemVerilog unique, unique0, and...
2017-02-23 Clifford WolfPreserve string parameters
2017-02-23 Clifford WolfAdded SystemVerilog support for ++ and --
2017-02-14 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-14 Clifford WolfFix incorrect "incompatible re-declaration of wire...
2017-02-11 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-11 Clifford WolfAdd support for verific mem initialization
2017-02-11 Clifford WolfFix another stupid bug in the same line
2017-02-11 Clifford WolfAdd verific support for initialized variables
2017-02-11 Clifford WolfImprove handling of Verific warnings and error messages
2017-02-11 Clifford WolfFix extremely stupid typo
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Clifford WolfAdd checker support to verilog front-end
2017-02-09 Clifford WolfAdd "rand" and "rand const" verific support
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-08 Clifford WolfAdd SV "rand" and "const rand" support
2017-02-08 Clifford WolfAdd PSL parser mode to verific front-end
2017-02-06 Clifford WolfAdd "read_blif -wideports"
2017-02-04 Clifford WolfFurther improve cover() support
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2017-02-04 Clifford WolfAdd assert/assume support to verific front-end
2017-01-31 Clifford WolfMerge branch 'opt_compare_pr' of https://github.com...
2017-01-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-01-17 Clifford WolfAdd "enum" and "typedef" lexer support
2017-01-15 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-01-15 Clifford WolfFix bug in AstNode::mem2reg_as_needed_pass2()
2017-01-05 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-01-05 Clifford WolfFixed handling of local memories in functions
2017-01-04 Clifford WolfAdded handling of local memories and error for local...
2017-01-03 Clifford WolfAdded Verilog $rtoi and $itor support
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-17 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-15 Clifford WolfAdded "verilog_defines" command
2016-11-28 Clifford WolfAdded support for macros as include file names
2016-11-28 Clifford WolfBugfix in "read_verilog -D NAME=VAL" handling
2016-11-15 Clifford WolfAdded support for hierarchical defparams
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v...
2016-11-04 Clifford WolfFixed anonymous genblock object names
2016-11-01 Clifford WolfSome fixes in handling of signed arrays
2016-10-22 Clifford WolfAdded avail params to ilang format, check module params...
2016-10-19 Clifford WolfNo limit for length of lines in BLIF front-end
2016-10-14 Clifford WolfAdded $anyseq cell type
2016-10-14 Clifford WolfAdded $global_clock verilog syntax support for creating...
2016-10-11 Clifford WolfAdded $ff and $_FF_ cell types
2016-09-23 Clifford WolfAdded liberty parser support for types within cell...
2016-09-23 Clifford WolfMerge branch 'master' of https://github.com/brouhaha...
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