Merge remote-tracking branch 'origin/master' into xaig
[yosys.git] / frontends /
2019-02-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-02-21 Eddie HungMerge branch 'clifford/dffsrfix' of https://github...
2019-02-21 Eddie Hungread_aiger to not do -purge for clean
2019-02-21 Eddie Hunglut/not/and suffix to be ${lut,not,and}
2019-02-21 Eddie Hungread_aiger to also rename 0 index lut when wideports
2019-02-20 Eddie Hungread_aiger: new naming fixes
2019-02-20 Eddie Hungread_aiger to name wires with internal name, less likel...
2019-02-19 Eddie HungSame for ascii AIGERs too
2019-02-19 Eddie Hungread_aiger to cope with non-unique POs
2019-02-19 Eddie HungMerge branch 'master' into xaig
2019-02-19 Eddie Hungread_aiger to create sane $lut names, and rename when...
2019-02-19 Eddie HungAdd comment
2019-02-19 Eddie HungGet rid of boost dep, fix the FIXMEs for Win32?
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-17 Eddie HungIn read_xaiger, do not construct ConstEval for every LUT
2019-02-17 Eddie Hungread_aiger to ignore output = input of same wire; also...
2019-02-16 Eddie Hungread_aiger to disable log_debug
2019-02-16 Eddie Hungread_xaiger() to use f.read() not readsome()
2019-02-16 Eddie Hungread_aiger() to cope with constant outputs, mixed widep...
2019-02-15 Eddie Hungread_aiger with more asserts, and call clean
2019-02-14 Eddie HungLeave FIXME for clean
2019-02-14 Eddie HungUse module->addLut()
2019-02-14 Eddie HungUse ConstEval to compute LUT masks
2019-02-13 Eddie HungMerge remote-tracking branch 'origin/read_aiger' into...
2019-02-13 Eddie HungMerge https://github.com/YosysHQ/yosys into xaig
2019-02-13 Clifford WolfFix sign handling of real constants
2019-02-12 Eddie HungAdd support for read_aiger -wideports
2019-02-12 Eddie HungAdd support for read_aiger -map
2019-02-12 Eddie HungParse 'm' in xaiger
2019-02-12 Eddie HungMerge branch 'read_aiger' of github.com:eddiehung/yosys...
2019-02-12 Eddie HungUse module->add{Not,And}Gate() functions
2019-02-11 Eddie HungAdd read_xaiger
2019-02-11 Eddie HungDo not break for constraints
2019-02-11 Eddie HungNo increment line_count for binary ANDs
2019-02-11 Eddie HungDo not ignore newline after AND in binary AIG
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-08 Eddie HungaddDff -> addDffGate as per @daveshah1
2019-02-08 Eddie HungFix tabulation
2019-02-08 Eddie Hung-module_name arg to go before -clk_name
2019-02-08 Eddie HungAdd missing "[options]" to read_blif help
2019-02-08 Eddie HungAllow module name to be determined by argument too
2019-02-08 Eddie HungRefactor into AigerReader class
2019-02-08 Eddie HungParse binary AIG files
2019-02-08 Eddie HungRefactor to parse_aiger_header()
2019-02-08 Eddie HungAdd comment
2019-02-08 Eddie HungHandle reset logic in latches
2019-02-08 Eddie HungChange literal vars from int to unsigned
2019-02-08 Eddie HungCreate clk outside of latch loop
2019-02-08 Eddie HungHandle latch symbols too
2019-02-08 Eddie HungRemove return after log_error
2019-02-08 Eddie HungAdd support for symbol tables
2019-02-08 Eddie HungStub for binary AIGER
2019-02-06 Eddie HungRefactor
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungWIP
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire
2019-01-05 Clifford WolfBugfix in Verilog string handling
2019-01-04 Clifford WolfMerge pull request #777 from mmicko/achronix_cell_sim_fix
2019-01-04 Clifford WolfRemove -m32 Verific eval lib build instructions
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfImprove VerificImporter support for writes to asymmetri...
2019-01-02 Clifford WolfFix VerificImporter asymmetric memories error message
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-23 Clifford WolfMerge pull request #761 from whitequark/proc_clean_partial
2018-12-23 Clifford WolfAdd "read_ilang -[no]overwrite"
2018-12-22 Clifford WolfMerge pull request #757 from whitequark/manual_mem
2018-12-19 Clifford WolfMerge pull request #752 from Icenowy/anlogic-lut-cost
2018-12-19 Clifford WolfMerge pull request #753 from Icenowy/anlogic-makefile-fix
2018-12-19 Clifford WolfMerge pull request #749 from Icenowy/anlogic-dram-fix
2018-12-18 Clifford WolfMerge pull request #748 from makaimann/add-btor-ops
2018-12-18 Clifford WolfFix segfault in AST simplify
2018-12-18 Clifford WolfImprove src tagging (using names and attrs) of cells...
2018-12-17 Clifford WolfMerge pull request #746 from Icenowy/anlogic-dram
2018-12-17 Clifford WolfMerge pull request #742 from whitequark/changelog
2018-12-17 Clifford WolfMerge pull request #741 from whitequark/ilang_slice_sigspec
2018-12-16 whitequarkread_ilang: allow slicing sigspecs.
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt
2018-12-16 Clifford WolfMerge pull request #723 from whitequark/synth_ice40_map...
2018-12-16 Clifford WolfMerge pull request #722 from whitequark/rename_src
2018-12-16 Clifford WolfMerge pull request #720 from whitequark/master
2018-12-14 Sylvain Munautverilog_parser: Properly handle recursion when processi...
2018-12-06 Clifford WolfVerific updates
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-24 Sylvain MunautMake return value of $clog2 signed
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-09 Clifford WolfSet Verific flag vhdl_support_variable_slice=1
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