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greenpak4_counters: Changed generation of primitive names so that the absorbed regist...
[yosys.git]
/
frontends
/
2017-06-07
Clifford Wolf
Fix generation of vlogtb output in yosys-smtbmc for...
tree
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commitdiff
2017-06-01
Clifford Wolf
Fix handling of Verilog ~& and ~| operators
tree
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commitdiff
2017-04-30
Clifford Wolf
Add support for localparam in module header
tree
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commitdiff
2017-04-26
Clifford Wolf
Add support for `resetall compiler directive
tree
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commitdiff
2017-03-14
Clifford Wolf
Fix verilog pre-processor for multi-level relative...
tree
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commitdiff
2017-03-01
Clifford Wolf
Allow $anyconst, etc. in non-formal SV mode
tree
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commitdiff
2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
tree
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commitdiff
2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
tree
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commitdiff
2017-02-24
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-02-23
Clifford Wolf
Add support for SystemVerilog unique, unique0, and...
tree
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commitdiff
2017-02-23
Clifford Wolf
Preserve string parameters
tree
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commitdiff
2017-02-23
Clifford Wolf
Added SystemVerilog support for ++ and --
tree
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commitdiff
2017-02-14
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-02-14
Clifford Wolf
Fix incorrect "incompatible re-declaration of wire...
tree
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commitdiff
2017-02-11
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-02-11
Clifford Wolf
Add support for verific mem initialization
tree
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commitdiff
2017-02-11
Clifford Wolf
Fix another stupid bug in the same line
tree
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commitdiff
2017-02-11
Clifford Wolf
Add verific support for initialized variables
tree
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commitdiff
2017-02-11
Clifford Wolf
Improve handling of Verific warnings and error messages
tree
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commitdiff
2017-02-11
Clifford Wolf
Fix extremely stupid typo
tree
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commitdiff
2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
tree
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commitdiff
2017-02-09
Clifford Wolf
Add checker support to verilog front-end
tree
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commitdiff
2017-02-09
Clifford Wolf
Add "rand" and "rand const" verific support
tree
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commitdiff
2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-02-08
Clifford Wolf
Add SV "rand" and "const rand" support
tree
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commitdiff
2017-02-08
Clifford Wolf
Add PSL parser mode to verific front-end
tree
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commitdiff
2017-02-06
Clifford Wolf
Add "read_blif -wideports"
tree
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commitdiff
2017-02-04
Clifford Wolf
Further improve cover() support
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commitdiff
2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
tree
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commitdiff
2017-02-04
Clifford Wolf
Add assert/assume support to verific front-end
tree
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commitdiff
2017-01-31
Clifford Wolf
Merge branch 'opt_compare_pr' of https://github.com...
tree
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commitdiff
2017-01-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-01-17
Clifford Wolf
Add "enum" and "typedef" lexer support
tree
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commitdiff
2017-01-15
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-01-15
Clifford Wolf
Fix bug in AstNode::mem2reg_as_needed_pass2()
tree
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commitdiff
2017-01-05
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2017-01-05
Clifford Wolf
Fixed handling of local memories in functions
tree
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commitdiff
2017-01-04
Clifford Wolf
Added handling of local memories and error for local...
tree
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commitdiff
2017-01-03
Clifford Wolf
Added Verilog $rtoi and $itor support
tree
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commitdiff
2016-12-23
Andrew Zonenberg
Merge pull request #1 from azonenberg-hk/master
tree
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commitdiff
2016-12-17
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
tree
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commitdiff
2016-12-15
Clifford Wolf
Added "verilog_defines" command
tree
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commitdiff
2016-11-28
Clifford Wolf
Added support for macros as include file names
tree
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commitdiff
2016-11-28
Clifford Wolf
Bugfix in "read_verilog -D NAME=VAL" handling
tree
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commitdiff
2016-11-15
Clifford Wolf
Added support for hierarchical defparams
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commitdiff
2016-11-15
Clifford Wolf
Remember global declarations and defines accross read_v...
tree
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commitdiff
2016-11-04
Clifford Wolf
Fixed anonymous genblock object names
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commitdiff
2016-11-01
Clifford Wolf
Some fixes in handling of signed arrays
tree
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commitdiff
2016-10-22
Clifford Wolf
Added avail params to ilang format, check module params...
tree
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commitdiff
2016-10-19
Clifford Wolf
No limit for length of lines in BLIF front-end
tree
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commitdiff
2016-10-14
Clifford Wolf
Added $anyseq cell type
tree
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commitdiff
2016-10-14
Clifford Wolf
Added $global_clock verilog syntax support for creating...
tree
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commitdiff
2016-10-11
Clifford Wolf
Added $ff and $_FF_ cell types
tree
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commitdiff
2016-09-23
Clifford Wolf
Added liberty parser support for types within cell...
tree
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commitdiff
2016-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/brouhaha...
tree
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commitdiff
2016-09-18
Clifford Wolf
Added $past, $stable, $rose, $fell SVA functions
tree
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commitdiff
2016-09-18
Clifford Wolf
Added support for bus interfaces to "read_liberty ...
tree
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commitdiff
2016-09-06
Clifford Wolf
Added assertpmux
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commitdiff
2016-09-06
Clifford Wolf
Bugfix in parsing of BLIF latch init values
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commitdiff
2016-09-06
Clifford Wolf
Avoid creation of bogus initial blocks for assert/assum...
tree
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commitdiff
2016-08-30
Clifford Wolf
Added $anyconst support to yosys-smtbmc
tree
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commitdiff
2016-08-30
Clifford Wolf
Removed $aconst cell type
tree
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commitdiff
2016-08-28
Clifford Wolf
Removed $predict again
tree
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commitdiff
2016-08-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2016-08-26
Clifford Wolf
Merge pull request #215 from frznchckn/to_upstream
tree
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commitdiff
2016-08-26
Clifford Wolf
Added read_verilog -norestrict -assume-asserts
tree
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commitdiff
2016-08-25
Clifford Wolf
Improved verilog parser errors
tree
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commitdiff
2016-08-24
Clifford Wolf
Added SV "restrict" keyword
tree
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commitdiff
2016-08-22
Clifford Wolf
Fixed bug with memories that do not have a down-to...
tree
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commitdiff
2016-08-21
Clifford Wolf
Another bugfix in mem2reg code
tree
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commitdiff
2016-08-21
Clifford Wolf
Minor improvements to AstNode::dumpAst() and AstNode...
tree
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commitdiff
2016-08-20
Clifford Wolf
Fixed finish_addr handling in $readmemh/$readmemb
tree
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commitdiff
2016-08-19
Clifford Wolf
Optimize memory address port width in wreduce and memor...
tree
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commitdiff
2016-08-10
Clifford Wolf
Only allow posedge/negedge with 1 bit wide signals
tree
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commitdiff
2016-08-06
Clifford Wolf
Fixed bug in parsing real constants
tree
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commitdiff
2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2016-07-27
Clifford Wolf
Added $anyconst and $aconst
tree
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commitdiff
2016-07-27
Clifford Wolf
Added "read_verilog -dump_rtlil"
tree
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commitdiff
2016-07-25
Clifford Wolf
Fixed a verilog parser memory leak
tree
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commitdiff
2016-07-25
Clifford Wolf
Fixed parsing of empty positional cell ports
tree
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commitdiff
2016-07-23
Clifford Wolf
No tristate warning message for "read_verilog -lib"
tree
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commitdiff
2016-07-21
Clifford Wolf
Using $initstate in "initial assume" and "initial assert"
tree
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commitdiff
2016-07-21
Clifford Wolf
Added $initstate cell type and vlog function
tree
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commitdiff
2016-07-21
Clifford Wolf
After reading the SV spec, using non-standard predict...
tree
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commitdiff
2016-07-13
Clifford Wolf
Added basic support for $expect cells
tree
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commitdiff
2016-07-08
Clifford Wolf
Fixed mem assignment in left-hand-side concatenation
tree
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commitdiff
2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
tree
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commitdiff
2016-06-21
Clifford Wolf
Merge pull request #181 from rubund/input_logic_allowed
tree
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commitdiff
2016-06-20
Ruben Undheim
Allow defining input ports as "input logic" in SystemVe...
tree
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commitdiff
2016-06-19
Clifford Wolf
Merge branch 'sv_packages' of https://github.com/rubund...
tree
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commitdiff
2016-06-18
Ruben Undheim
A few modifications after pull request comments
tree
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commitdiff
2016-06-18
Clifford Wolf
Added "read_blif -sop"
tree
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commitdiff
2016-06-18
Ruben Undheim
Added support for SystemVerilog packages with localpara...
tree
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commitdiff
2016-06-17
Clifford Wolf
Added $sop cell type and "abc -sop"
tree
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commitdiff
2016-05-27
Clifford Wolf
Fixed procedural assignments to non-unique lvalues...
tree
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commitdiff
2016-05-27
Clifford Wolf
Fixed access-after-delete bug in mem2reg code
tree
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commitdiff
2016-05-27
Clifford Wolf
fixed typos in error messages
tree
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commitdiff
2016-05-20
Clifford Wolf
Merge branch 'master' of https://github.com/Kmanfi...
tree
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commitdiff
2016-05-20
Clifford Wolf
Small improvements in Verilog front-end docs
tree
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