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Sort ctrl signals in fsm_extract
[yosys.git]
/
frontends
/
2013-07-27
Clifford Wolf
Added "design" command (-reset, -save, -load)
tree
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commitdiff
2013-07-12
Clifford Wolf
More fixes in ternary op sign handling
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commitdiff
2013-07-11
Clifford Wolf
Fixed sign handling in ternary operator
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commitdiff
2013-07-11
Clifford Wolf
Another vloghammer related bugfix
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commitdiff
2013-07-09
Clifford Wolf
Fixed sign propagation in bit-wise operators
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commitdiff
2013-07-09
Clifford Wolf
More fixes in ast expression sign/width handling
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commitdiff
2013-07-09
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2013-07-09
Clifford Wolf
Major redesign of expr width/sign detecion (verilog...
tree
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commitdiff
2013-07-07
Clifford Wolf
Fixed another bug found using vloghammer
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commitdiff
2013-07-07
Clifford Wolf
Fixed AST_CONSTANT node generation
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commitdiff
2013-07-04
Clifford Wolf
Added defparam support to Verilog/AST frontend
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commitdiff
2013-06-13
Clifford Wolf
More fixes for bugs found using xsthammer
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commitdiff
2013-06-11
Clifford Wolf
Further improved and extended xsthammer
tree
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commitdiff
2013-06-10
Clifford Wolf
Sign-extension related fixes in SatGen and AST frontend
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commitdiff
2013-06-10
Clifford Wolf
Fixes and improvements in AST const folding
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commitdiff
2013-06-10
Clifford Wolf
Enabled AST/Verilog front-end optimizations per default
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commitdiff
2013-06-07
Clifford Wolf
Added SAT generator and simple sat_solve command
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commitdiff
2013-05-24
Clifford Wolf
Added log_assert() api
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commitdiff
2013-05-23
Clifford Wolf
Fixed memory leak in ilang frontend
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commitdiff
2013-05-19
Clifford Wolf
Merge pull request #6 from hansiglaser/master
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commitdiff
2013-05-19
Johann Glaser
added option '-Dname[=definition]' to command 'read_ver...
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commitdiff
2013-05-16
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2013-05-16
Clifford Wolf
Merge branch 'bugfix'
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commitdiff
2013-05-16
Clifford Wolf
Fixed synthesis of functions in latched blocks
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commitdiff
2013-05-07
Clifford Wolf
Added support for verilog === operator
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commitdiff
2013-04-26
Clifford Wolf
Fixed handling of positional module parameters
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commitdiff
2013-04-26
Clifford Wolf
Only use sha1 checksums for names of parametric modules...
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commitdiff
2013-04-13
Clifford Wolf
Fixed a bug in AST frontend for cases with non-blocking...
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commitdiff
2013-03-31
Clifford Wolf
Now only use value from "initial" when no matching...
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commitdiff
2013-03-31
Clifford Wolf
Added AST_INITIAL (before verilog "initial" was mapped...
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commitdiff
2013-03-28
Clifford Wolf
Implemented proper handling of stub placeholder modules
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commitdiff
2013-03-26
Clifford Wolf
Improvements and bugfixes for generate blocks with...
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commitdiff
2013-03-26
Clifford Wolf
Fixed handling of unconditional generate blocks
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commitdiff
2013-03-25
Clifford Wolf
Added nosync attribute and some async reset related...
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commitdiff
2013-03-24
Clifford Wolf
Added mem2reg option to verilog frontend
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commitdiff
2013-03-24
Clifford Wolf
Another fix in mem2reg ast simplify logic
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commitdiff
2013-03-24
Clifford Wolf
Improved mem2reg handling in ast simplifier
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commitdiff
2013-03-23
Clifford Wolf
Tiny fixes to verilog parser
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commitdiff
2013-03-01
Clifford Wolf
Added help messages to ilang and verilog frontends
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commitdiff
2013-02-27
Clifford Wolf
Moved stand-alone libs to libs/ directory and added...
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commitdiff
2013-02-26
Clifford Wolf
Added support for verilog genblock[index].member syntax
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commitdiff
2013-01-16
Clifford Wolf
Added support for "always @(*)"
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commitdiff
2013-01-05
Clifford Wolf
added .gitignore files
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commitdiff
2013-01-05
Clifford Wolf
initial import
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commitdiff