| 2014-08-23 |
Clifford Wolf | Removed compatbility.{h,cc}: Not using open_memstream... |
tree | commitdiff |
| 2014-08-23 |
Clifford Wolf | Changed frontend-api from FILE to std::istream |
tree | commitdiff |
| 2014-08-22 |
Clifford Wolf | Added emscripten (emcc) support to build system and... |
tree | commitdiff |
| 2014-08-22 |
Clifford Wolf | Added support for non-standard <plugin>:<c_name> DPI... |
tree | commitdiff |
| 2014-08-22 |
Clifford Wolf | Archibald Rust and Clifford Wolf: ffi-based dpi_call() |
tree | commitdiff |
| 2014-08-21 |
Clifford Wolf | Fixed small memory leak in ast simplify |
tree | commitdiff |
| 2014-08-21 |
Clifford Wolf | Added support for DPI function with different names... |
tree | commitdiff |
| 2014-08-21 |
Clifford Wolf | Added AstNode::asInt() |
tree | commitdiff |
| 2014-08-21 |
Clifford Wolf | Fixed memory leak in DPI function calls |
tree | commitdiff |
| 2014-08-21 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
tree | commitdiff |
| 2014-08-21 |
Clifford Wolf | Added Verilog/AST support for DPI functions (dpi_call... |
tree | commitdiff |
| 2014-08-21 |
Clifford Wolf | Added support for global tasks and functions |
tree | commitdiff |
| 2014-08-18 |
Clifford Wolf | Added "via_celltype" attribute on task/func |
tree | commitdiff |
| 2014-08-17 |
Clifford Wolf | Added const folding of AST_CASE to AST simplifier |
tree | commitdiff |
| 2014-08-17 |
Clifford Wolf | Improved AST ProcessGenerator performance |
tree | commitdiff |
| 2014-08-16 |
Clifford Wolf | Use stackmap<> in AST ProcessGenerator |
tree | commitdiff |
| 2014-08-16 |
Clifford Wolf | Added module->uniquify() |
tree | commitdiff |
| 2014-08-16 |
Clifford Wolf | AST ProcessGenerator: replaced subst_*_{from,to} with... |
tree | commitdiff |
| 2014-08-15 |
Clifford Wolf | Renamed $_INV_ cell type to $_NOT_ |
tree | commitdiff |
| 2014-08-14 |
Clifford Wolf | Fixed bug in "read_verilog -ignore_redef" |
tree | commitdiff |
| 2014-08-14 |
Clifford Wolf | Added RTLIL::SigSpec::to_sigbit_map() |
tree | commitdiff |
| 2014-08-14 |
Clifford Wolf | Changed the AST genWidthRTLIL subst interface to use... |
tree | commitdiff |
| 2014-08-14 |
Clifford Wolf | Fixed line numbers when using here-doc macros |
tree | commitdiff |
| 2014-08-14 |
Clifford Wolf | Fixed handling of task outputs |
tree | commitdiff |
| 2014-08-14 |
Clifford Wolf | Added module->ports |
tree | commitdiff |
| 2014-08-13 |
Clifford Wolf | Added support for non-standard """ macro bodies |
tree | commitdiff |
| 2014-08-12 |
Clifford Wolf | Fixed building verific bindings |
tree | commitdiff |
| 2014-08-07 |
Clifford Wolf | Also allow "module foobar(input foo, output bar, .... |
tree | commitdiff |
| 2014-08-06 |
Clifford Wolf | Added AST_MULTIRANGE (arrays with more than 1 dimension) |
tree | commitdiff |
| 2014-08-05 |
Clifford Wolf | Improved scope resolution of local regs in Verilog... |
tree | commitdiff |
| 2014-08-05 |
Clifford Wolf | Fixed AST handling of variables declared inside a funct... |
tree | commitdiff |
| 2014-08-04 |
Clifford Wolf | Added support for non-standard "module mod_name(..... |
tree | commitdiff |
| 2014-08-02 |
Clifford Wolf | More bugfixes related to new RTLIL::IdString |
tree | commitdiff |
| 2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
tree | commitdiff |
| 2014-08-01 |
Clifford Wolf | Preparations for RTLIL::IdString redesign: cleanup... |
tree | commitdiff |
| 2014-08-01 |
Clifford Wolf | Replaced sha1 implementation |
tree | commitdiff |
| 2014-07-31 |
Clifford Wolf | Fixed build of verific bindings |
tree | commitdiff |
| 2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
tree | commitdiff |
| 2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module... |
tree | commitdiff |
| 2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
tree | commitdiff |
| 2014-07-30 |
Clifford Wolf | Fixed counting verilog line numbers for "// synopsys... |
tree | commitdiff |
| 2014-07-29 |
Clifford Wolf | Fixed Verilog pre-processor for files with no trailing... |
tree | commitdiff |
| 2014-07-29 |
Clifford Wolf | Added $shift and $shiftx cell types (needed for correct... |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Removed left over debug code |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Fixed part selects of parameters |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Set results of out-of-bounds static bit/part select... |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Fixed RTLIL code generator for part select of parameter |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Fixed width detection for part selects |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Added support for "upto" wires to Verilog front- and... |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Added wire->upto flag for signals such as "wire [0... |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
tree | commitdiff |
| 2014-07-28 |
Clifford Wolf | Fixed signdness detection of expressions with bit-... |
tree | commitdiff |
| 2014-07-27 |
Clifford Wolf | Added proper Design->addModule interface |
tree | commitdiff |
| 2014-07-27 |
Clifford Wolf | Fixed verific bindings for new RTLIL api |
tree | commitdiff |
| 2014-07-27 |
Clifford Wolf | Fixed ilang parser for new RTLIL API |
tree | commitdiff |
| 2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
tree | commitdiff |
| 2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
tree | commitdiff |
| 2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
tree | commitdiff |
| 2014-07-26 |
Clifford Wolf | Changed a lot of code to the new RTLIL::Wire constructors |
tree | commitdiff |
| 2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
tree | commitdiff |
| 2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
tree | commitdiff |
| 2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
tree | commitdiff |
| 2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
tree | commitdiff |
| 2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
tree | commitdiff |
| 2014-07-25 |
Clifford Wolf | Use only module->addCell() and module->remove() to... |
tree | commitdiff |
| 2014-07-25 |
Clifford Wolf | Fixed two memory leaks in ast simplify |
tree | commitdiff |
| 2014-07-25 |
Clifford Wolf | Updated verific build/test instructions |
tree | commitdiff |
| 2014-07-24 |
Clifford Wolf | Replaced more old SigChunk programming patterns |
tree | commitdiff |
| 2014-07-24 |
Clifford Wolf | Added "make PRETTY=1" |
tree | commitdiff |
| 2014-07-23 |
Clifford Wolf | Various fixes in Verific frontend for new RTLIL API |
tree | commitdiff |
| 2014-07-23 |
Clifford Wolf | Various small fixes (from gcc compiler warnings) |
tree | commitdiff |
| 2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::optimize() |
tree | commitdiff |
| 2014-07-23 |
Clifford Wolf | Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL... |
tree | commitdiff |
| 2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
tree | commitdiff |
| 2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
tree | commitdiff |
| 2014-07-22 |
Clifford Wolf | SigSpec refactoring: More cleanups of old SigSpec use... |
tree | commitdiff |
| 2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::chunks... |
tree | commitdiff |
| 2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::size()... |
tree | commitdiff |
| 2014-07-22 |
Clifford Wolf | SigSpec refactoring: using the accessor functions every... |
tree | commitdiff |
| 2014-07-22 |
Clifford Wolf | SigSpec refactoring: renamed chunks and width to __chun... |
tree | commitdiff |
| 2014-07-22 |
Clifford Wolf | Fixed ilang parsing of process attributes |
tree | commitdiff |
| 2014-07-22 |
Clifford Wolf | Fixed make rules for ilang parser |
tree | commitdiff |
| 2014-07-21 |
Clifford Wolf | Added "autoidx" statement to ilang file format |
tree | commitdiff |
| 2014-07-21 |
Clifford Wolf | Replaced depricated NEW_WIRE macro with module->addWire... |
tree | commitdiff |
| 2014-07-21 |
Clifford Wolf | Removed deprecated module->new_wire() |
tree | commitdiff |
| 2014-07-17 |
Clifford Wolf | Implemented dynamic bit-/part-select for memory writes |
tree | commitdiff |
| 2014-07-17 |
Clifford Wolf | Added support for bit/part select to mem2reg rewriter |
tree | commitdiff |
| 2014-07-17 |
Clifford Wolf | Added support for constant bit- or part-select for... |
tree | commitdiff |
| 2014-07-16 |
Clifford Wolf | Added "inout" ports support to read_liberty |
tree | commitdiff |
| 2014-07-16 |
Clifford Wolf | Set blackbox attribute in "read_liberty -lib" |
tree | commitdiff |
| 2014-07-16 |
Clifford Wolf | Fixed spelling of "direction" in read_liberty messages |
tree | commitdiff |
| 2014-07-16 |
Clifford Wolf | Merged new $mem/$memwr WR_EN interface |
tree | commitdiff |
| 2014-07-16 |
Clifford Wolf | changes in verilog frontend for new $mem/$memwr WR_EN... |
tree | commitdiff |
| 2014-07-12 |
Clifford Wolf | Added passing of various options to vhdl2verilog |
tree | commitdiff |
| 2014-07-11 |
Clifford Wolf | Fixed processing of initial values for block-local... |
tree | commitdiff |
| 2014-07-02 |
Clifford Wolf | fixed parsing of constant with comment between size... |
tree | commitdiff |
| 2014-06-25 |
Clifford Wolf | Fixed handling of mixed real/int ternary expressions |
tree | commitdiff |
| 2014-06-24 |
Clifford Wolf | More found_real-related fixes to AstNode::detectSignWid... |
tree | commitdiff |
| 2014-06-21 |
Clifford Wolf | fixed signdness detection for expressions with reals |
tree | commitdiff |
| 2014-06-17 |
Clifford Wolf | Added AstNode::MEM2REG_FL_CMPLX_LHS |
tree | commitdiff |
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