x86: Updated align branch tests for Darwin and i686-pc-elf
[binutils-gdb.git] / gas / testsuite / gas / riscv /
2020-01-01 Alan ModraUpdate year range in copyright notice of binutils files
2019-11-28 Andrew Burgessgas/riscv: Produce version 3 DWARF CIE by default
2019-11-28 Andrew Burgessgas: Check for overflow on return column in version...
2019-11-28 Andrew Burgessbinutils/gas/riscv: Add DWARF register numbers for...
2019-11-13 Jim WilsonRISC-V: Support the INSN_CLASS.*F.* classes for .insn...
2019-08-26 Kito ChengRISC-V: Improve li expansion for better code density.
2019-07-30 Jim WilsonRISC-V: Fix minor issues with FP csr instructions.
2019-07-05 Jim WilsonKito's 5-part patch set to improve .insn support.
2019-05-30 Jim WilsonRISC-V: Fix lui argument parsing.
2019-01-16 Jim WilsonDon't emit vendor attribute section if there is no...
2019-01-16 Jim WilsonRISC-V: Support ELF attribute for gas and readelf.
2019-01-01 Alan ModraUpdate year range in copyright notice of binutils files
2018-12-11 Jim WilsonRISC-V: Don't segfault for two regs in auipc or lui.
2018-12-07 Jim WilsonRISC-V: Fix 4-arg add parsing.
2018-12-03 Jim WilsonRISC-V: Accept version, supervisor ext and more than...
2018-11-27 Jim WilsonRISC-V: Add .insn CA support.
2018-10-02 Palmer DabbeltRISC-V: Add fence.tso instruction
2018-09-17 Jim WilsonRISC-V: bge[u] should get higher priority than ble[u].
2018-09-15 Alan Modragas run_dump_test rename stderr and error-output
2018-08-31 Jim WilsonRISC-V: Correct the requirement of compressed floating...
2018-08-23 Jim WilsonRISC-V: Reject empty rouding mode and fence operand.
2018-06-20 Sebastian HuberRISC-V: Accept constant operands in la and lla
2018-05-24 Jim WilsonRISC-V: Fix .align handling when .option norelax.
2018-05-08 Jim WilsonRISC-V: Add missing hint instructions from RV128I.
2018-04-20 Jim WilsonRISC-V: Add new option -mrelax/-mno-relax.
2018-03-16 Jim WilsonRISC-V: Emit better warning for unknown CSR.
2018-03-14 Jim WilsonMissing testcase files for last commit.
2018-01-15 Jim WilsonRISC-V: Add support for addi that compresses to c.nop.
2018-01-10 Jim WilsonRISC-V: Disassemble x0 based addresses as 0.
2018-01-04 Jim WilsonRISC-V: Add 2 missing privileged registers.
2018-01-03 Alan ModraUpdate year range in copyright notice of binutils files
2017-12-28 Jim WilsonRISC-V: Add missing privileged spec registers.
2017-12-20 Jim WilsonRISC-V: Add compressed instruction hints, and a few...
2017-12-13 Jim WilsonAdd missing RISC-V fsrmi and fsflagsi instructions.
2017-11-29 Jim WilsonFix riscv malloc error on small alignment after norvc.
2017-11-28 Jim WilsonCompress loads/stores with implicit 0 offset.
2017-11-07 Jim WilsonRISC-V: Fix riscv g++ testsuite EH failures.
2017-11-07 Palmer DabbeltRISC-V: Add satp as an alias for sptbr
2017-10-24 Andrew WatermanRISC-V: Fix disassembly of c.addi4spn, c.addi16sp,...
2017-10-24 Andrew WatermanRISC-V: Only relax to C.LUI when imm != 0 and rd !...
2017-09-27 Nick CliftonAdd support for the new names of the RISC-V fmv.x.s...
2017-01-02 Alan ModraUpdate year range in copyright notice of all files.
2016-11-01 Nick CliftonAdd support for RISC-V architecture.