git.libre-soc.org Git - gram.git/history - gram/simulation/simsoctb.v

2020-07-10	Jean THOMAS	Fix timings in simulation to prevent tDLLK errors	blob \| commitdiff \| raw
2020-07-10	Jean THOMAS	Add POR start/end logging in simsoc testbench	blob \| commitdiff \| raw \| diff to current
2020-07-08	Jean THOMAS	Fix clock input	blob \| commitdiff \| raw \| diff to current
2020-07-08	Jean THOMAS	cke => clk_en in SoC testbench	blob \| commitdiff \| raw \| diff to current
2020-07-06	Jean THOMAS	Add write transactions in the simulation testbench	blob \| commitdiff \| raw \| diff to current
2020-07-02	Jean THOMAS	Add missing command issue strobe for ZQ calibration	blob \| commitdiff \| raw \| diff to current
2020-07-02	Jean THOMAS	Fix register addresses, add missing command_issue strobe	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Fix merge	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Rework indentation and add Wishbone tests	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Add Wishbone interaction code	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Add Wishbone interaction code	blob \| commitdiff \| raw \| diff to current
2020-06-29	Jean THOMAS	Define simulation time as a parameter	blob \| commitdiff \| raw \| diff to current
2020-06-29	Jean THOMAS	Set DRAM's CK_N to low	blob \| commitdiff \| raw \| diff to current
2020-06-29	Jean THOMAS	Set UART RX to 1'b1	blob \| commitdiff \| raw \| diff to current
2020-06-26	Jean THOMAS	Add testbench for SoC simulation	blob \| commitdiff \| raw \| diff to current