Remove steerer_sel function
[gram.git] / gram / simulation /
2020-08-04 Jean THOMASFix simulation to support diff pairs
2020-07-30 Jean THOMASSet default value for dram_rst
2020-07-30 Jean THOMASFix typo
2020-07-29 Jean THOMASEnsure sync2x and sync are in sync (fixes #20)
2020-07-28 Jean THOMASMake R/W tests more intense
2020-07-28 Jean THOMASAdd speedtest_write task
2020-07-28 Jean THOMASRemove simticks
2020-07-28 Jean THOMASAdd speedtest_read task in testbench
2020-07-28 Jean THOMASRemove unused resources
2020-07-27 Jean THOMASRemove reference to UART
2020-07-27 Jean THOMASWire directly to the Wishbone bus, making simulations...
2020-07-23 Jean THOMASFix platform code for simulation
2020-07-22 Jean THOMASFix granularity and sel in UARTBridge
2020-07-21 Jean THOMASUse 0x00BA0BAB instead of 0x12345678 for better readability
2020-07-20 Jean THOMASUse PinsN when possible (fixes #27)
2020-07-17 Jean THOMASUse XDR for ba pins
2020-07-17 Jean THOMASUse XDR for address pins
2020-07-17 Jean THOMASUse nMigen's XDR for DDR clk
2020-07-17 Jean THOMASReduce delay between wishbone_write
2020-07-17 Jean THOMASLog DRAM commands
2020-07-17 Jean THOMASPut proc_rmdead after proc_mux
2020-07-17 Jean THOMASFix DQS_N errors
2020-07-17 Jean THOMASAdd more read transactions, add checks, ASAP
2020-07-16 Jean THOMASUse assertions in simsoc testbench
2020-07-16 Jean THOMASAdd logging and delays to the simulation to make it...
2020-07-16 Jean THOMASTweak yosys script
2020-07-16 Jean THOMASBackport modifications from example's CRG
2020-07-15 Jean THOMASMake Micron model read the mem_init.txt file
2020-07-15 Jean THOMASMake gram simulations faster
2020-07-15 Jean THOMASAdd initial memory content
2020-07-15 Jean THOMASIncrease UART bridge speed in simulation, decrease...
2020-07-15 Jean THOMASLog RAM signals
2020-07-13 Jean THOMASReduce POR duration
2020-07-13 Jean THOMASFix gearing and UART speed
2020-07-13 Jean THOMASAdd additional opt+clean and print stats
2020-07-10 Jean THOMASFix timings in simulation to prevent tDLLK errors
2020-07-10 Jean THOMASAdd POR start/end logging in simsoc testbench
2020-07-08 Jean THOMASMatch ECPIX-5 DRAM parameters in Micron's model
2020-07-08 Jean THOMASFix clock input
2020-07-08 Jean THOMAScke => clk_en in SoC testbench
2020-07-07 Jean THOMASFix CRG PLL parameters (fixing #23)
2020-07-06 Jean THOMASRename from cke to clk_en
2020-07-06 Jean THOMASAdd write transactions in the simulation testbench
2020-07-03 Jean THOMASUpdate CRG with parameters that work IRL
2020-07-03 Jean THOMASInvert condition in runsimcrg.sh
2020-07-03 Jean THOMASCheck if YOSYS env var is set and use it as YOSYS execu...
2020-07-03 Jean THOMASExclude DDRDLLA from tree
2020-07-03 Jean THOMASEnsure dramsync runs at 100Mhz, sync2x at 200Mhz
2020-07-03 Jean THOMASRemove DDRDLLA
2020-07-03 Jean THOMASUpdate simulation gitignore
2020-07-03 Jean THOMASUpdate gram simulation documentation
2020-07-03 Jean THOMASAdd cleaning pass
2020-07-03 Jean THOMASRework CRG simulation
2020-07-03 Jean THOMASExternalize CRG into its own file
2020-07-02 Jean THOMASFlatten specific parts of the designs
2020-07-02 Jean THOMASAdd missing command issue strobe for ZQ calibration
2020-07-02 Jean THOMASFix register addresses, add missing command_issue strobe
2020-07-02 Jean THOMASAdd DDRDLLA patch
2020-07-01 Jean THOMASFix merge
2020-07-01 Jean THOMASRework indentation and add Wishbone tests
2020-07-01 Jean THOMASAdd Wishbone interaction code
2020-07-01 Jean THOMASAdd Wishbone interaction code
2020-07-01 Jean THOMASFix Iverilog simulation
2020-07-01 Jean THOMASGenerate ilang file
2020-06-30 Jean THOMASBuild nMigen gateware in a specific folder
2020-06-30 Jean THOMASRemove LED code in CRG
2020-06-30 Jean THOMASRemove Minerva dependency
2020-06-29 Jean THOMASDefine simulation time as a parameter
2020-06-29 Jean THOMASDefine PLL's PHASELOADREG input
2020-06-29 Jean THOMASUse -n option in vvp to enable CTRL+C
2020-06-29 Jean THOMASFix PLL instanciation code for CRG simulation
2020-06-29 Jean THOMASDump whole module
2020-06-29 Jean THOMASSet DRAM's CK_N to low
2020-06-29 Jean THOMASFix CRG, revert to resetful sync domain
2020-06-29 Jean THOMASSet UART RX to 1'b1
2020-06-29 Jean THOMASAdd -Wall to simulations
2020-06-26 Jean THOMASAdd testbench for SoC simulation
2020-06-26 Jean THOMASUse FST instead of VCD
2020-06-26 Jean THOMASExclude .fst files
2020-06-26 Jean THOMASAdd DDRSoC simulation
2020-06-26 Jean THOMASAdd gitignore for simulation folder
2020-06-26 Jean THOMASFix PLL code
2020-06-26 Jean THOMASAdd DRAM model
2020-06-25 Jean THOMASFix typo
2020-06-25 Jean THOMASAdd simulation code