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Rename VCD file output
[gram.git]
/
gram
/
simulation
/
2020-07-10
Jean THOMAS
Fix timings in simulation to prevent tDLLK errors
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commitdiff
2020-07-10
Jean THOMAS
Add POR start/end logging in simsoc testbench
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commitdiff
2020-07-08
Jean THOMAS
Match ECPIX-5 DRAM parameters in Micron's model
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commitdiff
2020-07-08
Jean THOMAS
Fix clock input
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commitdiff
2020-07-08
Jean THOMAS
cke => clk_en in SoC testbench
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commitdiff
2020-07-07
Jean THOMAS
Fix CRG PLL parameters (fixing #23)
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commitdiff
2020-07-06
Jean THOMAS
Rename from cke to clk_en
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commitdiff
2020-07-06
Jean THOMAS
Add write transactions in the simulation testbench
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commitdiff
2020-07-03
Jean THOMAS
Update CRG with parameters that work IRL
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commitdiff
2020-07-03
Jean THOMAS
Invert condition in runsimcrg.sh
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commitdiff
2020-07-03
Jean THOMAS
Check if YOSYS env var is set and use it as YOSYS execu...
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commitdiff
2020-07-03
Jean THOMAS
Exclude DDRDLLA from tree
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commitdiff
2020-07-03
Jean THOMAS
Ensure dramsync runs at 100Mhz, sync2x at 200Mhz
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commitdiff
2020-07-03
Jean THOMAS
Remove DDRDLLA
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commitdiff
2020-07-03
Jean THOMAS
Update simulation gitignore
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commitdiff
2020-07-03
Jean THOMAS
Update gram simulation documentation
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commitdiff
2020-07-03
Jean THOMAS
Add cleaning pass
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commitdiff
2020-07-03
Jean THOMAS
Rework CRG simulation
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commitdiff
2020-07-03
Jean THOMAS
Externalize CRG into its own file
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commitdiff
2020-07-02
Jean THOMAS
Flatten specific parts of the designs
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commitdiff
2020-07-02
Jean THOMAS
Add missing command issue strobe for ZQ calibration
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commitdiff
2020-07-02
Jean THOMAS
Fix register addresses, add missing command_issue strobe
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commitdiff
2020-07-02
Jean THOMAS
Add DDRDLLA patch
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commitdiff
2020-07-01
Jean THOMAS
Fix merge
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commitdiff
2020-07-01
Jean THOMAS
Rework indentation and add Wishbone tests
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commitdiff
2020-07-01
Jean THOMAS
Add Wishbone interaction code
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commitdiff
2020-07-01
Jean THOMAS
Add Wishbone interaction code
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commitdiff
2020-07-01
Jean THOMAS
Fix Iverilog simulation
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commitdiff
2020-07-01
Jean THOMAS
Generate ilang file
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commitdiff
2020-06-30
Jean THOMAS
Build nMigen gateware in a specific folder
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commitdiff
2020-06-30
Jean THOMAS
Remove LED code in CRG
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commitdiff
2020-06-30
Jean THOMAS
Remove Minerva dependency
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commitdiff
2020-06-29
Jean THOMAS
Define simulation time as a parameter
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commitdiff
2020-06-29
Jean THOMAS
Define PLL's PHASELOADREG input
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commitdiff
2020-06-29
Jean THOMAS
Use -n option in vvp to enable CTRL+C
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commitdiff
2020-06-29
Jean THOMAS
Fix PLL instanciation code for CRG simulation
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commitdiff
2020-06-29
Jean THOMAS
Dump whole module
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commitdiff
2020-06-29
Jean THOMAS
Set DRAM's CK_N to low
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commitdiff
2020-06-29
Jean THOMAS
Fix CRG, revert to resetful sync domain
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commitdiff
2020-06-29
Jean THOMAS
Set UART RX to 1'b1
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commitdiff
2020-06-29
Jean THOMAS
Add -Wall to simulations
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commitdiff
2020-06-26
Jean THOMAS
Add testbench for SoC simulation
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commitdiff
2020-06-26
Jean THOMAS
Use FST instead of VCD
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commitdiff
2020-06-26
Jean THOMAS
Exclude .fst files
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commitdiff
2020-06-26
Jean THOMAS
Add DDRSoC simulation
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commitdiff
2020-06-26
Jean THOMAS
Add gitignore for simulation folder
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commitdiff
2020-06-26
Jean THOMAS
Fix PLL code
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commitdiff
2020-06-26
Jean THOMAS
Add DRAM model
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commitdiff
2020-06-25
Jean THOMAS
Fix typo
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commitdiff
2020-06-25
Jean THOMAS
Add simulation code
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commitdiff