Add tests for core/refresher.py
[gram.git] / gram / simulation /
2020-07-02 Jean THOMASFlatten specific parts of the designs
2020-07-02 Jean THOMASAdd missing command issue strobe for ZQ calibration
2020-07-02 Jean THOMASFix register addresses, add missing command_issue strobe
2020-07-02 Jean THOMASAdd DDRDLLA patch
2020-07-01 Jean THOMASFix merge
2020-07-01 Jean THOMASRework indentation and add Wishbone tests
2020-07-01 Jean THOMASAdd Wishbone interaction code
2020-07-01 Jean THOMASAdd Wishbone interaction code
2020-07-01 Jean THOMASFix Iverilog simulation
2020-07-01 Jean THOMASGenerate ilang file
2020-06-30 Jean THOMASBuild nMigen gateware in a specific folder
2020-06-30 Jean THOMASRemove LED code in CRG
2020-06-30 Jean THOMASRemove Minerva dependency
2020-06-29 Jean THOMASDefine simulation time as a parameter
2020-06-29 Jean THOMASDefine PLL's PHASELOADREG input
2020-06-29 Jean THOMASUse -n option in vvp to enable CTRL+C
2020-06-29 Jean THOMASFix PLL instanciation code for CRG simulation
2020-06-29 Jean THOMASDump whole module
2020-06-29 Jean THOMASSet DRAM's CK_N to low
2020-06-29 Jean THOMASFix CRG, revert to resetful sync domain
2020-06-29 Jean THOMASSet UART RX to 1'b1
2020-06-29 Jean THOMASAdd -Wall to simulations
2020-06-26 Jean THOMASAdd testbench for SoC simulation
2020-06-26 Jean THOMASUse FST instead of VCD
2020-06-26 Jean THOMASExclude .fst files
2020-06-26 Jean THOMASAdd DDRSoC simulation
2020-06-26 Jean THOMASAdd gitignore for simulation folder
2020-06-26 Jean THOMASFix PLL code
2020-06-26 Jean THOMASAdd DRAM model
2020-06-25 Jean THOMASFix typo
2020-06-25 Jean THOMASAdd simulation code