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Connect dramcore to SoC bus in ECPIX-5 example
[gram.git] / gram /
2020-06-08 Jean THOMASRename LiteDRAM to gram tree | commitdiff
2020-06-08 Jean THOMASUse CSRPrefixProxy for exposing CSR tree | commitdiff
2020-06-08 Jean THOMASAdd CSRPrefixProxy to gram.compat tree | commitdiff
2020-06-08 Jean THOMASFix bugs in ECP5DDRPHY instanciation tree | commitdiff
2020-06-08 Jean THOMASMigrate FIFO frontend from Migen to nMigen tree | commitdiff
2020-06-08 Jean THOMASRework DFI interface code tree | commitdiff
2020-06-08 Jean THOMASClean unused code tree | commitdiff
2020-06-08 Jean THOMASAdd copyright tree | commitdiff
2020-06-08 Jean THOMASRemove setaddr for submodule instanciation tree | commitdiff
2020-06-08 Jean THOMASFix multiple drive issue tree | commitdiff
2020-06-08 Jean THOMASAdd copyright tree | commitdiff
2020-06-05 Jean THOMASRemove bandwidth meter tree | commitdiff
2020-06-05 Jean THOMASFix direction in stream assignment tree | commitdiff
2020-06-05 Jean THOMASFix typo tree | commitdiff
2020-06-05 Jean THOMASRemove useless variable tree | commitdiff
2020-06-05 Jean THOMASFix signal drive error tree | commitdiff
2020-06-05 Jean THOMASFix multi-driven signals in refresher tree | commitdiff
2020-06-04 Jean THOMASBugfixing tree | commitdiff
2020-06-04 Jean THOMASCorrect nMigen transition bugs tree | commitdiff
2020-06-04 Jean THOMASMore nMigen conversion and fixes tree | commitdiff
2020-06-03 Jean THOMASInitial commit tree | commitdiff