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[binutils-gdb.git] / include / opcode / riscv-opc.h

2020-06-30	Nelson Chu	RISC-V: Support debug and float CSR as the unprivileged...	blob \| commitdiff \| raw
2020-06-30	Nelson Chu	RISC-V: Cleanup the include/opcode/riscv-opc.h.	blob \| commitdiff \| raw \| diff to current
2020-06-12	Nelson Chu	RISC-V: Drop the privileged spec v1.9 support.	blob \| commitdiff \| raw \| diff to current
2020-05-20	Nelson Chu	[PATCH v2 0/9] RISC-V: Support version controling for...	blob \| commitdiff \| raw \| diff to current
2020-03-30	Nelson Chu	RISC-V: Update CSR to privileged spec 1.11.	blob \| commitdiff \| raw \| diff to current
2020-02-21	Nelson Chu	RISC-V: Support the ISA-dependent CSR checking.	blob \| commitdiff \| raw \| diff to current
2018-10-02	Palmer Dabbelt	RISC-V: Add fence.tso instruction	blob \| commitdiff \| raw \| diff to current
2018-05-08	Jim Wilson	RISC-V: Add missing hint instructions from RV128I.	blob \| commitdiff \| raw \| diff to current
2018-01-04	Jim Wilson	RISC-V: Add 2 missing privileged registers.	blob \| commitdiff \| raw \| diff to current
2017-12-28	Jim Wilson	RISC-V: Add missing privileged spec registers.	blob \| commitdiff \| raw \| diff to current
2017-11-07	Palmer Dabbelt	RISC-V: Add satp as an alias for sptbr	blob \| commitdiff \| raw \| diff to current
2017-03-31	Andrew Waterman	RISC-V: Add physical memory protection CSRs	blob \| commitdiff \| raw \| diff to current
2017-02-24	Andrew Waterman	Add new counter-enable CSRs	blob \| commitdiff \| raw \| diff to current
2017-02-15	Andrew Waterman	Add SFENCE.VMA instruction	blob \| commitdiff \| raw \| diff to current
2017-01-03	Kito Cheng	Add support for the Q extension to the RISCV ISA.	blob \| commitdiff \| raw \| diff to current
2016-11-01	Nick Clifton	Add support for RISC-V architecture.	blob \| commitdiff \| raw \| diff to current

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