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x86: Adjust linker tests for --disable-separate-code
[binutils-gdb.git]
/
include
/
opcode
/
riscv-opc.h
2021-11-17
Nelson Chu
RISC-V: Support rvv extension with released version...
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2021-11-16
jiawei
RISC-V: Scalar crypto instructions and operand set.
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2021-10-07
Philipp Tomsich
RISC-V: Add support for Zbs instructions
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2021-03-16
Kuan-Lin Chen
RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions
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2021-02-05
Nelson Chu
RISC-V: PR27348, Remove obsolete Xcustom support.
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2021-02-04
Nelson Chu
RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instruct...
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2021-01-15
Nelson Chu
RISC-V: Comments tidy and improvement.
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2021-01-07
Philipp Tomsich
RISC-V: Add pause hint instruction.
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2021-01-07
Claire Xenia Wolf
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instr...
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2021-01-01
Alan Modra
Update year range in copyright notice of binutils files
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2020-06-30
Nelson Chu
RISC-V: Support debug and float CSR as the unprivileged...
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2020-06-30
Nelson Chu
RISC-V: Cleanup the include/opcode/riscv-opc.h.
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2020-06-12
Nelson Chu
RISC-V: Drop the privileged spec v1.9 support.
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2020-05-20
Nelson Chu
[PATCH v2 0/9] RISC-V: Support version controling for...
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2020-03-30
Nelson Chu
RISC-V: Update CSR to privileged spec 1.11.
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2020-02-21
Nelson Chu
RISC-V: Support the ISA-dependent CSR checking.
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2018-10-02
Palmer Dabbelt
RISC-V: Add fence.tso instruction
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2018-05-08
Jim Wilson
RISC-V: Add missing hint instructions from RV128I.
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2018-01-04
Jim Wilson
RISC-V: Add 2 missing privileged registers.
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2017-12-28
Jim Wilson
RISC-V: Add missing privileged spec registers.
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2017-11-07
Palmer Dabbelt
RISC-V: Add satp as an alias for sptbr
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2017-03-31
Andrew Waterman
RISC-V: Add physical memory protection CSRs
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2017-02-24
Andrew Waterman
Add new counter-enable CSRs
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2017-02-15
Andrew Waterman
Add SFENCE.VMA instruction
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2017-01-03
Kito Cheng
Add support for the Q extension to the RISCV ISA.
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2016-11-01
Nick Clifton
Add support for RISC-V architecture.
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