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Regularize control flow in dirty-bit test
[riscv-tests.git]
/
isa
/
rv32ui
/
Makefrag
2016-08-30
Andrew Waterman
Add missing RV32 slt[i]u tests
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2016-07-12
Andrew Waterman
Remove vestigial j instruction test; improve jal test
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2016-06-22
Howard Mao
separate ua and um tests from ui tests
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2016-05-23
Andrew Waterman
Enable LR/SC tests, even for uniprocessors
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2016-05-01
Andrew Waterman
ERET -> xRET; new memory map
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2016-03-15
Andrew Waterman
Merge branch 'priv-1.9'
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2016-03-14
Andrew Waterman
More RV32 tests
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2015-03-16
Yunsup Lee
revamp vector tests with new privileged spec, and add...
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2014-08-28
Christopher Celio
Added "simple" test to rv32ui.
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2014-02-11
Adam Izraelevitz
Merge branch 'master' of github.com:ucb-bar/riscv-tests
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2014-01-24
Eric Love
Done with rv32ui asm test ports
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2014-01-24
Eric Love
Fixed srl, srli
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2014-01-24
Eric Love
srl and srai
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2014-01-23
Eric Love
First round of rv32ui asm tests
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2013-08-12
Sebastien Mirolo
Merge branch 'master' of git://github.com/ucb-bar/riscv...
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2013-07-26
Andrew Waterman
Remove JALR static hints
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2013-04-30
Andrew Waterman
add first RV32 tests
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