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Added $lcu cell type
[yosys.git]
/
kernel
/
consteval.h
2014-09-08
Clifford Wolf
Added $lcu cell type
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2014-09-08
Clifford Wolf
Added "$fa" cell type
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2014-09-06
Clifford Wolf
Added $macc eval model
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2014-09-03
Clifford Wolf
Fixes in $alu SAT- and eval-models
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2014-09-01
Clifford Wolf
Added ConstEval model for $alu cells
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2014-08-16
Clifford Wolf
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...
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2014-08-14
Clifford Wolf
RIP $safe_pmux
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Added RTLIL::Cell::has(portname)
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-24
Clifford Wolf
Replaced more old SigChunk programming patterns
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::expand() method
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2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::chunks...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-01-14
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
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2014-01-03
Clifford Wolf
Fixed SAT and ConstEval undef handling for $pmux and...
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2013-11-06
Clifford Wolf
Fixed handling of undef values in MUX select input...
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2013-01-05
Clifford Wolf
initial import
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