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Merge branch 'koriakin/xc7nocarrymux' into xaig
[yosys.git]
/
kernel
/
rtlil.cc
2019-02-21
Clifford Wolf
Merge pull request #786 from YosysHQ/pmgen
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2019-02-20
Clifford Wolf
Add FF support to wreduce
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2019-02-11
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2018-12-31
Clifford Wolf
Merge pull request #766 from Icenowy/anlogic-latches
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2018-12-23
Clifford Wolf
Merge pull request #761 from whitequark/proc_clean_partial
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2018-12-23
whitequark
proc_clean: remove any empty cases if all cases use...
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2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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2018-10-13
Ruben Undheim
Documentation improvements etc.
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2018-10-12
Ruben Undheim
Support for 'modports' for System Verilog interfaces
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2018-10-12
Ruben Undheim
Synthesis support for SystemVerilog interfaces
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2018-08-20
Benedikt Tutzer
added some checks if python is enabled to make sure...
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2018-08-13
Benedikt Tutzer
Added Wrappers for:
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2018-07-10
Benedikt Tutzer
added destructors for wires and cells
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2018-07-09
Benedikt Tutzer
removed debug output
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2018-07-09
Benedikt Tutzer
multiple designs can now exist independent from each...
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2018-02-23
Clifford Wolf
Merge branch 'forall'
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2018-02-23
Clifford Wolf
Add $allconst and $allseq cell types
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2018-01-05
Clifford Wolf
Merge pull request #479 from Fatsie/latch_without_data
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2018-01-05
Clifford Wolf
Bugfix in hierarchy handling of blackbox module ports
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2017-12-14
Clifford Wolf
Merge branch 'master' into btor-ng
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2017-12-14
Clifford Wolf
Add RTLIL::Const::is_fully_ones()
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2017-12-14
Clifford Wolf
Add SigSpec::is_fully_ones()
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2017-12-12
Clifford Wolf
Add SigSpec::is_fully_ones()
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2017-09-09
Clifford Wolf
Add src arguments to all cell creator helper functions
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2017-09-01
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-09-01
Clifford Wolf
Merge branch 'ChipScan-master'
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2017-09-01
Clifford Wolf
Update more stuff to use get_src_attribute() and set_sr...
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2017-08-31
Andrew Zonenberg
Merge branch 'counter-extraction' of github.com:azonenb...
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2017-08-30
Andrew Zonenberg
Merge branch 'master' of https://github.com/cliffordwol...
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2017-08-30
Jason Lowdermilk
Merge remote-tracking branch 'upstream/master'
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2017-08-30
Jason Lowdermilk
fix indent level
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2017-08-30
Clifford Wolf
Merge pull request #397 from azonenberg/gpak-libfixes
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2017-08-30
Clifford Wolf
Add {get,set}_src_attribute() methods on RTLIL::AttrObject
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2017-08-29
Jason Lowdermilk
Add support for source line tracking through synthesis...
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2017-08-18
Clifford Wolf
Merge branch 'sim'
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2017-08-18
Clifford Wolf
Add Const methods is_fully_zero(), is_fully_def(),...
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2017-05-17
Clifford Wolf
Add $_ANDNOT_ and $_ORNOT_ gates
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2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
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2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
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2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
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2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
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2017-01-31
Clifford Wolf
Merge branch 'opt_compare_pr' of https://github.com...
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2017-01-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-01-25
Clifford Wolf
Fix RTLIL::Memory::start_offset initialization
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2017-01-01
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-12-31
Clifford Wolf
Bugfix in RTLIL::SigSpec::remove2()
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2016-11-15
Clifford Wolf
Remember global declarations and defines accross read_v...
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2016-10-14
Clifford Wolf
Added $anyseq cell type
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2016-10-11
Clifford Wolf
Added $ff and $_FF_ cell types
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2016-09-07
Clifford Wolf
Improvements in assertpmux
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2016-08-30
Clifford Wolf
Removed $aconst cell type
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2016-08-28
Clifford Wolf
Removed $predict again
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2016-08-27
Clifford Wolf
Fixed handling of transparent bram rd ports on ROMs
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2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-27
Clifford Wolf
Added $anyconst and $aconst
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2016-07-21
Clifford Wolf
Added $initstate cell type and vlog function
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2016-07-21
Clifford Wolf
After reading the SV spec, using non-standard predict...
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2016-07-13
Clifford Wolf
Added basic support for $expect cells
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-06-19
Clifford Wolf
Merge branch 'sv_packages' of https://github.com/rubund...
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2016-06-18
Ruben Undheim
A few modifications after pull request comments
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2016-06-18
Ruben Undheim
Added support for SystemVerilog packages with localpara...
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2016-06-17
Clifford Wolf
Improved support for $sop cells
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2016-06-17
Clifford Wolf
Added $sop cell type and "abc -sop"
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2016-02-02
Clifford Wolf
Added addBufGate module method
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2016-01-31
Clifford Wolf
Merge branch 'rtlil_remove2_speedup' of https://github...
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2016-01-31
Rick Altherr
rtlil: Improve performance of SigSpec::extract(SigSpec...
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2016-01-31
Rick Altherr
rtlil: speed up SigSpec::sort_and_unify()
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2016-01-31
Rick Altherr
rtlil: improve performance of SigSpec::replace(SigSpec...
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2016-01-31
Rick Altherr
rtlil: improve performance of SigSpec::remove2(SigSpec...
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2016-01-31
Clifford Wolf
Merge branch 'rtlil_remove2_speedup' of https://github...
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2016-01-30
Rick Altherr
rtlil: rewrite remove2() to avoid copying
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2016-01-30
Rick Altherr
rtlil: duplicate remove2() for std::set<>
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-10-25
Clifford Wolf
Import more std:: stuff into Yosys namespace
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2015-10-24
Clifford Wolf
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit...
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2015-10-24
Clifford Wolf
Fixed driver conflict handling (various cmds)
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2015-10-24
Clifford Wolf
Fixed handling of driver-driver conflicts in wreduce
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2015-09-25
Clifford Wolf
Added read-enable to memory model
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2015-09-18
Clifford Wolf
Cosmetic fix in Module::addLut()
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2015-08-16
Clifford Wolf
Added $tribuf and $_TBUF_ cell types
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2015-08-12
Clifford Wolf
Merge pull request #70 from gaomy3832/bugfix
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2015-08-11
Clifford Wolf
Fixed handling of [a-fxz?] in decimal constants
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2015-07-31
Clifford Wolf
Added WORDS parameter to $meminit
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-06-29
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-06-29
Clifford Wolf
Added design->rename(module, new_name)
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2015-06-17
Clifford Wolf
Added "rename -top new_name"
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2015-06-11
Clifford Wolf
Fixed cstr_buf for std::string with small string optimi...
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2015-06-09
Clifford Wolf
Merge branch 'verilog-backend-memV2' of github.com...
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2015-06-08
Clifford Wolf
Fixed "avail_parameters" handling in module clone/copy
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2015-04-29
Clifford Wolf
Added $eq/$neq -> $logic_not/$reduce_bool optimization
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2015-04-24
Clifford Wolf
Improved attributes API and handling of "src" attributes
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2015-04-05
Clifford Wolf
Avoid parameter values with size 0 ($mem cells)
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