Merge branch 'koriakin/xc7nocarrymux' into xaig
[yosys.git] / kernel / rtlil.cc
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen
2019-02-20 Clifford WolfAdd FF support to wreduce
2019-02-11 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-23 Clifford WolfMerge pull request #761 from whitequark/proc_clean_partial
2018-12-23 whitequarkproc_clean: remove any empty cases if all cases use...
2018-12-18 Jim LawsonMerge remote-tracking branch 'upstream/master'
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-13 Ruben UndheimDocumentation improvements etc.
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-08-20 Benedikt Tutzeradded some checks if python is enabled to make sure...
2018-08-13 Benedikt TutzerAdded Wrappers for:
2018-07-10 Benedikt Tutzeradded destructors for wires and cells
2018-07-09 Benedikt Tutzerremoved debug output
2018-07-09 Benedikt Tutzermultiple designs can now exist independent from each...
2018-02-23 Clifford WolfMerge branch 'forall'
2018-02-23 Clifford WolfAdd $allconst and $allseq cell types
2018-01-05 Clifford WolfMerge pull request #479 from Fatsie/latch_without_data
2018-01-05 Clifford WolfBugfix in hierarchy handling of blackbox module ports
2017-12-14 Clifford WolfMerge branch 'master' into btor-ng
2017-12-14 Clifford WolfAdd RTLIL::Const::is_fully_ones()
2017-12-14 Clifford WolfAdd SigSpec::is_fully_ones()
2017-12-12 Clifford WolfAdd SigSpec::is_fully_ones()
2017-09-09 Clifford WolfAdd src arguments to all cell creator helper functions
2017-09-01 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-09-01 Clifford WolfMerge branch 'ChipScan-master'
2017-09-01 Clifford WolfUpdate more stuff to use get_src_attribute() and set_sr...
2017-08-31 Andrew ZonenbergMerge branch 'counter-extraction' of github.com:azonenb...
2017-08-30 Andrew ZonenbergMerge branch 'master' of https://github.com/cliffordwol...
2017-08-30 Jason LowdermilkMerge remote-tracking branch 'upstream/master'
2017-08-30 Jason Lowdermilkfix indent level
2017-08-30 Clifford WolfMerge pull request #397 from azonenberg/gpak-libfixes
2017-08-30 Clifford WolfAdd {get,set}_src_attribute() methods on RTLIL::AttrObject
2017-08-29 Jason LowdermilkAdd support for source line tracking through synthesis...
2017-08-18 Clifford WolfMerge branch 'sim'
2017-08-18 Clifford WolfAdd Const methods is_fully_zero(), is_fully_def(),...
2017-05-17 Clifford WolfAdd $_ANDNOT_ and $_ORNOT_ gates
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2017-01-31 Clifford WolfMerge branch 'opt_compare_pr' of https://github.com...
2017-01-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-01-25 Clifford WolfFix RTLIL::Memory::start_offset initialization
2017-01-01 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-31 Clifford WolfBugfix in RTLIL::SigSpec::remove2()
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v...
2016-10-14 Clifford WolfAdded $anyseq cell type
2016-10-11 Clifford WolfAdded $ff and $_FF_ cell types
2016-09-07 Clifford WolfImprovements in assertpmux
2016-08-30 Clifford WolfRemoved $aconst cell type
2016-08-28 Clifford WolfRemoved $predict again
2016-08-27 Clifford WolfFixed handling of transparent bram rd ports on ROMs
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-27 Clifford WolfAdded $anyconst and $aconst
2016-07-21 Clifford WolfAdded $initstate cell type and vlog function
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund...
2016-06-18 Ruben UndheimA few modifications after pull request comments
2016-06-18 Ruben UndheimAdded support for SystemVerilog packages with localpara...
2016-06-17 Clifford WolfImproved support for $sop cells
2016-06-17 Clifford WolfAdded $sop cell type and "abc -sop"
2016-02-02 Clifford WolfAdded addBufGate module method
2016-01-31 Clifford WolfMerge branch 'rtlil_remove2_speedup' of https://github...
2016-01-31 Rick Altherrrtlil: Improve performance of SigSpec::extract(SigSpec...
2016-01-31 Rick Altherrrtlil: speed up SigSpec::sort_and_unify()
2016-01-31 Rick Altherrrtlil: improve performance of SigSpec::replace(SigSpec...
2016-01-31 Rick Altherrrtlil: improve performance of SigSpec::remove2(SigSpec...
2016-01-31 Clifford WolfMerge branch 'rtlil_remove2_speedup' of https://github...
2016-01-30 Rick Altherrrtlil: rewrite remove2() to avoid copying
2016-01-30 Rick Altherrrtlil: duplicate remove2() for std::set<>
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-10-25 Clifford WolfImport more std:: stuff into Yosys namespace
2015-10-24 Clifford Wolfrenamed SigSpec::to_single_sigbit() to SigSpec::as_bit...
2015-10-24 Clifford WolfFixed driver conflict handling (various cmds)
2015-10-24 Clifford WolfFixed handling of driver-driver conflicts in wreduce
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-09-18 Clifford WolfCosmetic fix in Module::addLut()
2015-08-16 Clifford WolfAdded $tribuf and $_TBUF_ cell types
2015-08-12 Clifford WolfMerge pull request #70 from gaomy3832/bugfix
2015-08-11 Clifford WolfFixed handling of [a-fxz?] in decimal constants
2015-07-31 Clifford WolfAdded WORDS parameter to $meminit
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-06-29 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-06-29 Clifford WolfAdded design->rename(module, new_name)
2015-06-17 Clifford WolfAdded "rename -top new_name"
2015-06-11 Clifford WolfFixed cstr_buf for std::string with small string optimi...
2015-06-09 Clifford WolfMerge branch 'verilog-backend-memV2' of github.com...
2015-06-08 Clifford WolfFixed "avail_parameters" handling in module clone/copy
2015-04-29 Clifford WolfAdded $eq/$neq -> $logic_not/$reduce_bool optimization
2015-04-24 Clifford WolfImproved attributes API and handling of "src" attributes
2015-04-05 Clifford WolfAvoid parameter values with size 0 ($mem cells)
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