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Added $assert cell
[yosys.git]
/
kernel
/
rtlil.cc
2014-01-19
Clifford Wolf
Added $assert cell
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2014-01-03
Clifford Wolf
Added RTLIL::SigSpec::optimized() API
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2014-01-02
Clifford Wolf
Added correct handling of $memwr priority
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2013-12-31
Clifford Wolf
Added additional checks for A_SIGNED == B_SIGNED for...
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2013-12-28
Clifford Wolf
Added $bu0 cell (for easy correct $eq/$ne mapping)
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2013-12-27
Clifford Wolf
Added support for non-const === and !== (for miter...
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2013-12-07
Clifford Wolf
Fixes and improvements in RTLIL::SigSpec::parse
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2013-12-04
Clifford Wolf
Replaced signed_parameters API with CONST_FLAG_SIGNED
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2013-12-04
Clifford Wolf
Replaced RTLIL::Const::str with generic decoder method
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2013-11-24
Clifford Wolf
Remove auto_wire framework (smarter than the verilog...
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2013-11-24
Clifford Wolf
Implemented correct handling of signed module parameters
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2013-11-22
Clifford Wolf
Massive performance improvement from refactoring RTLIL...
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2013-11-22
Clifford Wolf
Added SigBit struct and refactored RTLIL::SigSpec:...
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2013-11-10
Clifford Wolf
Added information on all internal cell types to interna...
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2013-11-09
Clifford Wolf
Improved user-friendliness of "sat" and "eval" expressi...
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2013-11-07
Clifford Wolf
Renamed extend_un0() to extend_u0() and use it in genrtlil
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2013-11-07
Clifford Wolf
Fixed type of sign extension in opt_const $eq/$ne handling
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2013-11-06
Clifford Wolf
Added eval -vloghammer_report mode
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2013-10-18
Clifford Wolf
Changed NEW_WIRE API to return the wire, not the signal
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2013-10-18
Clifford Wolf
Added RTLIL NEW_WIRE macro
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2013-07-27
Clifford Wolf
Added "design" command (-reset, -save, -load)
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2013-06-19
Clifford Wolf
Added "eval" pass
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2013-06-18
Clifford Wolf
Added RTLIL::Module::fixup_ports() API and RTLIL::...
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2013-06-02
Clifford Wolf
Added "dump" command (part ilang backend)
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2013-05-16
Clifford Wolf
Merge branch 'bugfix'
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2013-03-29
Clifford Wolf
Improved opt_share for reduce cells
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2013-03-26
Clifford Wolf
Create nice errors when calling RTLIL::Module::derive...
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2013-01-05
Clifford Wolf
initial import
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