2014-12-27 |
Clifford Wolf | More hashtable finetuning |
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2014-12-26 |
Clifford Wolf | Replaced std::unordered_set (nodict) with Yosys::pool |
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2014-12-26 |
Clifford Wolf | Replaced std::unordered_map as implementation for Yosys... |
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2014-12-26 |
Clifford Wolf | Added new_dict (hashmap.h) and re-enabled code coverage... |
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2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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2014-12-24 |
Clifford Wolf | Renamed extend() to extend_xx(), changed most users... |
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2014-12-11 |
Clifford Wolf | Added IdString::destruct_guard hack |
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2014-12-08 |
Clifford Wolf | Added bool constructors to SigBit and SigSpec |
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2014-12-08 |
Clifford Wolf | Added module->addDffe() and module->addDffeGate() |
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2014-12-08 |
Clifford Wolf | Added $dffe cell type |
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2014-12-08 |
Clifford Wolf | Added $_DFFE_??_ cell types |
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2014-11-09 |
Clifford Wolf | Added log_warning() API |
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2014-10-26 |
Clifford Wolf | Added support for $readmemh/$readmemb |
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2014-10-18 |
Clifford Wolf | Fixed various VS warnings |
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2014-10-17 |
Clifford Wolf | Various win32 / vs build fixes |
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2014-10-15 |
Clifford Wolf | Fixed RTLIL::SigSpec::parse() for out-of-range bit... |
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2014-10-10 |
Clifford Wolf | Renamed SIZE() to GetSize() because of name collision... |
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2014-10-03 |
Clifford Wolf | Added $_BUF_ cell type |
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2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2014-09-19 |
Clifford Wolf | Initialize RTLIL::Const from std::vector<bool> |
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2014-09-14 |
Clifford Wolf | Fixed monitor notifications for removed cell |
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2014-09-08 |
Clifford Wolf | Added $lcu cell type |
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2014-09-08 |
Clifford Wolf | Added "$fa" cell type |
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2014-09-06 |
Clifford Wolf | Added $macc cell type |
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2014-09-04 |
Clifford Wolf | Removed $bu0 cell type |
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2014-09-02 |
Clifford Wolf | Create a default selection stack in RTLIL::Design:... |
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2014-09-01 |
Clifford Wolf | Using std::vector<RTLIL::State> instead of RTLIL::Const... |
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2014-08-31 |
Clifford Wolf | Added $lut support in test_cell, techmap, satgen |
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2014-08-30 |
Clifford Wolf | Added design->scratchpad |
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2014-08-30 |
Clifford Wolf | Added $alu cell type |
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2014-08-30 |
Clifford Wolf | Fixed module->addPmux() |
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2014-08-24 |
Clifford Wolf | Added is_signed argument to SigSpec.as_int() and Const... |
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2014-08-23 |
Clifford Wolf | Changed backend-api from FILE to std::ostream |
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2014-08-22 |
Clifford Wolf | Added emscripten (emcc) support to build system and... |
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2014-08-21 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2014-08-19 |
Clifford Wolf | Added mod->addGate() methods for new gate types |
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2014-08-17 |
Clifford Wolf | Improved sig.remove2() performance |
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2014-08-16 |
Clifford Wolf | Added module->uniquify() |
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2014-08-16 |
Clifford Wolf | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_... |
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2014-08-15 |
Clifford Wolf | Renamed $lut ports to follow A-Y naming scheme |
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2014-08-15 |
Clifford Wolf | Renamed $_INV_ cell type to $_NOT_ |
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2014-08-14 |
Clifford Wolf | Added RTLIL::SigSpec::to_sigbit_map() |
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2014-08-14 |
Clifford Wolf | Added sig.{replace,remove,extract} variants for std... |
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2014-08-14 |
Clifford Wolf | Added module->ports |
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2014-08-14 |
Clifford Wolf | Refactoring of CellType class |
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2014-08-14 |
Clifford Wolf | RIP $safe_pmux |
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2014-08-05 |
Clifford Wolf | Added support for truncating of wires to wreduce pass |
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2014-08-02 |
Clifford Wolf | Bugfix in "techmap -extern" |
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2014-08-02 |
Clifford Wolf | Removed at() method from RTLIL::IdString |
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2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else |
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2014-08-02 |
Clifford Wolf | Improvements in new RTLIL::IdString implementation |
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2014-08-02 |
Clifford Wolf | Implemented new reference counting RTLIL::IdString |
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2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
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2014-08-01 |
Clifford Wolf | Added ModIndex helper class, some changes to RTLIL... |
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2014-08-01 |
Clifford Wolf | Packed SigBit::data and SigBit::offset in a union |
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2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
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2014-07-31 |
Clifford Wolf | Added RTLIL::Monitor |
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2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module... |
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2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
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2014-07-29 |
Clifford Wolf | Added "techmap -map %{design-name}" |
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2014-07-29 |
Clifford Wolf | Added $shift and $shiftx cell types (needed for correct... |
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2014-07-28 |
Clifford Wolf | Added wire->upto flag for signals such as "wire [0... |
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2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
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2014-07-28 |
Clifford Wolf | Added std::initializer_list<> constructor to SigSpec |
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2014-07-28 |
Clifford Wolf | Added cover() to all SigSpec constructors |
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2014-07-27 |
Clifford Wolf | Added proper Design->addModule interface |
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2014-07-27 |
Clifford Wolf | Added RTLIL::SigSpec::remove_const() handling of packed... |
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2014-07-27 |
Clifford Wolf | Added RTLIL::Module::wire(id) and cell(id) lookup functions |
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2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
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2014-07-27 |
Clifford Wolf | Added RTLIL::ObjIterator and RTLIL::ObjRange |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
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2014-07-26 |
Clifford Wolf | Changed more code to the new RTLIL::Wire constructors |
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2014-07-26 |
Clifford Wolf | Changed a lot of code to the new RTLIL::Wire constructors |
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2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
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2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
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2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
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2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
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2014-07-26 |
Clifford Wolf | Added some missing "const" in rtlil.h |
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2014-07-26 |
Clifford Wolf | Added RTLIL::Module::connections() |
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2014-07-26 |
Clifford Wolf | Added RTLIL::Module::connect(const RTLIL::SigSig&) |
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2014-07-26 |
Clifford Wolf | Automatically pack SigSpec on copy/assign |
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2014-07-26 |
Clifford Wolf | Added new RTLIL::Cell port access methods |
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2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
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2014-07-25 |
Clifford Wolf | Added copy-constructor-like module->addCell(name, other... |
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2014-07-25 |
Clifford Wolf | Use only module->addCell() and module->remove() to... |
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2014-07-25 |
Clifford Wolf | Added RTLIL::SigSpec is_chunk()/as_chunk() API |
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2014-07-25 |
Clifford Wolf | Fixed typo in cover id |
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2014-07-24 |
Clifford Wolf | Replaced more old SigChunk programming patterns |
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2014-07-24 |
Clifford Wolf | Some improvements in SigSpec packing/unpacking and... |
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2014-07-24 |
Clifford Wolf | Small changes regarding cover() and check() in SigSpec |
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2014-07-24 |
Clifford Wolf | Added support for YOSYS_COVER_FILE env variable |
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2014-07-24 |
Clifford Wolf | Added cover() calls to RTLIL::SigSpec methods |
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2014-07-23 |
Clifford Wolf | Added hashing to RTLIL::SigSpec relational and equal... |
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2014-07-23 |
Clifford Wolf | Disabled RTLIL::SigSpec::check() in release builds |
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2014-07-23 |
Clifford Wolf | Fixed release build |
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2014-07-23 |
Clifford Wolf | Added RTLIL::SigSpec::repeat() |
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2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::optimize() |
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2014-07-23 |
Clifford Wolf | Turned RTLIL::SigSpec::optimize() to a no-op: a packed... |
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2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::expand() method |
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