| 2016-11-15 |
Clifford Wolf | Remember global declarations and defines accross read_v... |
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| 2016-10-14 |
Clifford Wolf | Added $anyseq cell type |
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| 2016-10-11 |
Clifford Wolf | Added $ff and $_FF_ cell types |
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| 2016-09-07 |
Clifford Wolf | Improvements in assertpmux |
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| 2016-08-30 |
Clifford Wolf | Removed $aconst cell type |
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| 2016-08-28 |
Clifford Wolf | Removed $predict again |
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| 2016-08-27 |
Clifford Wolf | Fixed handling of transparent bram rd ports on ROMs |
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| 2016-07-30 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2016-07-27 |
Clifford Wolf | Added $anyconst and $aconst |
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| 2016-07-21 |
Clifford Wolf | Added $initstate cell type and vlog function |
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| 2016-07-21 |
Clifford Wolf | After reading the SV spec, using non-standard predict... |
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| 2016-07-13 |
Clifford Wolf | Added basic support for $expect cells |
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| 2016-07-08 |
Clifford Wolf | Merge branch 'yosys-0.5-vtr' of https://github.com... |
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| 2016-06-19 |
Clifford Wolf | Merge branch 'sv_packages' of https://github.com/rubund... |
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| 2016-06-18 |
Ruben Undheim | A few modifications after pull request comments |
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| 2016-06-18 |
Ruben Undheim | Added support for SystemVerilog packages with localpara... |
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| 2016-06-17 |
Clifford Wolf | Improved support for $sop cells |
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| 2016-06-17 |
Clifford Wolf | Added $sop cell type and "abc -sop" |
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| 2016-02-02 |
Clifford Wolf | Added addBufGate module method |
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| 2016-01-31 |
Clifford Wolf | Merge branch 'rtlil_remove2_speedup' of https://github... |
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| 2016-01-31 |
Rick Altherr | rtlil: Improve performance of SigSpec::extract(SigSpec... |
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| 2016-01-31 |
Rick Altherr | rtlil: speed up SigSpec::sort_and_unify() |
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| 2016-01-31 |
Rick Altherr | rtlil: improve performance of SigSpec::replace(SigSpec... |
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| 2016-01-31 |
Rick Altherr | rtlil: improve performance of SigSpec::remove2(SigSpec... |
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| 2016-01-31 |
Clifford Wolf | Merge branch 'rtlil_remove2_speedup' of https://github... |
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| 2016-01-30 |
Rick Altherr | rtlil: rewrite remove2() to avoid copying |
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| 2016-01-30 |
Rick Altherr | rtlil: duplicate remove2() for std::set<> |
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| 2015-12-07 |
Clifford Wolf | Merge pull request #108 from cseed/master |
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| 2015-10-25 |
Clifford Wolf | Import more std:: stuff into Yosys namespace |
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| 2015-10-24 |
Clifford Wolf | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit... |
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| 2015-10-24 |
Clifford Wolf | Fixed driver conflict handling (various cmds) |
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| 2015-10-24 |
Clifford Wolf | Fixed handling of driver-driver conflicts in wreduce |
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| 2015-09-25 |
Clifford Wolf | Added read-enable to memory model |
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| 2015-09-18 |
Clifford Wolf | Cosmetic fix in Module::addLut() |
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| 2015-08-16 |
Clifford Wolf | Added $tribuf and $_TBUF_ cell types |
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| 2015-08-12 |
Clifford Wolf | Merge pull request #70 from gaomy3832/bugfix |
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| 2015-08-11 |
Clifford Wolf | Fixed handling of [a-fxz?] in decimal constants |
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| 2015-07-31 |
Clifford Wolf | Added WORDS parameter to $meminit |
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| 2015-07-02 |
Clifford Wolf | Fixed trailing whitespaces |
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| 2015-06-29 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2015-06-29 |
Clifford Wolf | Added design->rename(module, new_name) |
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| 2015-06-17 |
Clifford Wolf | Added "rename -top new_name" |
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| 2015-06-11 |
Clifford Wolf | Fixed cstr_buf for std::string with small string optimi... |
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| 2015-06-09 |
Clifford Wolf | Merge branch 'verilog-backend-memV2' of github.com... |
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| 2015-06-08 |
Clifford Wolf | Fixed "avail_parameters" handling in module clone/copy |
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| 2015-04-29 |
Clifford Wolf | Added $eq/$neq -> $logic_not/$reduce_bool optimization |
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| 2015-04-24 |
Clifford Wolf | Improved attributes API and handling of "src" attributes |
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| 2015-04-05 |
Clifford Wolf | Avoid parameter values with size 0 ($mem cells) |
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| 2015-04-05 |
Clifford Wolf | Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types |
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| 2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2015-02-26 |
Clifford Wolf | Added $assume cell type |
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| 2015-02-14 |
Clifford Wolf | Added $meminit support to "memory" command |
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| 2015-02-14 |
Clifford Wolf | Added $meminit cell type |
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| 2015-02-07 |
Clifford Wolf | Added SigSpec::has_const() |
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| 2015-02-07 |
Clifford Wolf | Added cell->known(), cell->input(portname), cell->outpu... |
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| 2015-02-03 |
Clifford Wolf | Skip blackbox modules in design->selected_modules() |
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| 2015-01-31 |
Clifford Wolf | Added "equiv_make -blacklist <file> -encfile <file>" |
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| 2015-01-23 |
Clifford Wolf | Added dict/pool.sort() |
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| 2015-01-21 |
Clifford Wolf | Progress in equiv_simple |
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| 2015-01-19 |
Clifford Wolf | Added equiv_make command |
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| 2015-01-19 |
Clifford Wolf | Added $equiv cell type |
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| 2015-01-17 |
Clifford Wolf | Optimizing no-op cell->setPort() |
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| 2015-01-01 |
Clifford Wolf | Removed SigSpec::extend_xx() api |
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| 2014-12-30 |
Clifford Wolf | added hashlib::mkhash_init |
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| 2014-12-29 |
Clifford Wolf | Added "yosys -X" |
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| 2014-12-28 |
Clifford Wolf | Added mkhash_xorshift() |
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| 2014-12-28 |
Clifford Wolf | Added memhasher (yosys -M) |
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| 2014-12-28 |
Clifford Wolf | Fixed performance bug in object hashing |
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| 2014-12-28 |
Clifford Wolf | Renamed hashmap.h to hashlib.h, some related improvements |
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| 2014-12-27 |
Clifford Wolf | More dict/pool related changes |
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| 2014-12-27 |
Clifford Wolf | More hashtable finetuning |
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| 2014-12-26 |
Clifford Wolf | Replaced std::unordered_set (nodict) with Yosys::pool |
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| 2014-12-26 |
Clifford Wolf | Replaced std::unordered_map as implementation for Yosys... |
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| 2014-12-26 |
Clifford Wolf | Added new_dict (hashmap.h) and re-enabled code coverage... |
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| 2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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| 2014-12-24 |
Clifford Wolf | Renamed extend() to extend_xx(), changed most users... |
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| 2014-12-11 |
Clifford Wolf | Added IdString::destruct_guard hack |
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| 2014-12-08 |
Clifford Wolf | Added bool constructors to SigBit and SigSpec |
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| 2014-12-08 |
Clifford Wolf | Added module->addDffe() and module->addDffeGate() |
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| 2014-12-08 |
Clifford Wolf | Added $dffe cell type |
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| 2014-12-08 |
Clifford Wolf | Added $_DFFE_??_ cell types |
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| 2014-11-09 |
Clifford Wolf | Added log_warning() API |
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| 2014-10-26 |
Clifford Wolf | Added support for $readmemh/$readmemb |
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| 2014-10-18 |
Clifford Wolf | Fixed various VS warnings |
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| 2014-10-17 |
Clifford Wolf | Various win32 / vs build fixes |
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| 2014-10-15 |
Clifford Wolf | Fixed RTLIL::SigSpec::parse() for out-of-range bit... |
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| 2014-10-10 |
Clifford Wolf | Renamed SIZE() to GetSize() because of name collision... |
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| 2014-10-03 |
Clifford Wolf | Added $_BUF_ cell type |
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| 2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2014-09-19 |
Clifford Wolf | Initialize RTLIL::Const from std::vector<bool> |
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| 2014-09-14 |
Clifford Wolf | Fixed monitor notifications for removed cell |
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| 2014-09-08 |
Clifford Wolf | Added $lcu cell type |
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| 2014-09-08 |
Clifford Wolf | Added "$fa" cell type |
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| 2014-09-06 |
Clifford Wolf | Added $macc cell type |
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| 2014-09-04 |
Clifford Wolf | Removed $bu0 cell type |
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| 2014-09-02 |
Clifford Wolf | Create a default selection stack in RTLIL::Design:... |
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| 2014-09-01 |
Clifford Wolf | Using std::vector<RTLIL::State> instead of RTLIL::Const... |
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| 2014-08-31 |
Clifford Wolf | Added $lut support in test_cell, techmap, satgen |
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| 2014-08-30 |
Clifford Wolf | Added design->scratchpad |
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| 2014-08-30 |
Clifford Wolf | Added $alu cell type |
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