git.libre-soc.org Git - yosys.git/history

2014-12-24	Clifford Wolf	Renamed extend() to extend_xx(), changed most users...	blob \| commitdiff \| raw
2014-12-11	Clifford Wolf	Added IdString::destruct_guard hack	blob \| commitdiff \| raw \| diff to current
2014-12-08	Clifford Wolf	Added bool constructors to SigBit and SigSpec	blob \| commitdiff \| raw \| diff to current
2014-12-08	Clifford Wolf	Added module->addDffe() and module->addDffeGate()	blob \| commitdiff \| raw \| diff to current
2014-12-08	Clifford Wolf	Added $dffe cell type	blob \| commitdiff \| raw \| diff to current
2014-12-08	Clifford Wolf	Added $_DFFE_??_ cell types	blob \| commitdiff \| raw \| diff to current
2014-11-09	Clifford Wolf	Added log_warning() API	blob \| commitdiff \| raw \| diff to current
2014-10-26	Clifford Wolf	Added support for $readmemh/$readmemb	blob \| commitdiff \| raw \| diff to current
2014-10-18	Clifford Wolf	Fixed various VS warnings	blob \| commitdiff \| raw \| diff to current
2014-10-17	Clifford Wolf	Various win32 / vs build fixes	blob \| commitdiff \| raw \| diff to current
2014-10-15	Clifford Wolf	Fixed RTLIL::SigSpec::parse() for out-of-range bit...	blob \| commitdiff \| raw \| diff to current
2014-10-10	Clifford Wolf	Renamed SIZE() to GetSize() because of name collision...	blob \| commitdiff \| raw \| diff to current
2014-10-03	Clifford Wolf	Added $_BUF_ cell type	blob \| commitdiff \| raw \| diff to current
2014-09-22	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-09-19	Clifford Wolf	Initialize RTLIL::Const from std::vector<bool>	blob \| commitdiff \| raw \| diff to current
2014-09-14	Clifford Wolf	Fixed monitor notifications for removed cell	blob \| commitdiff \| raw \| diff to current
2014-09-08	Clifford Wolf	Added $lcu cell type	blob \| commitdiff \| raw \| diff to current
2014-09-08	Clifford Wolf	Added "$fa" cell type	blob \| commitdiff \| raw \| diff to current
2014-09-06	Clifford Wolf	Added $macc cell type	blob \| commitdiff \| raw \| diff to current
2014-09-04	Clifford Wolf	Removed $bu0 cell type	blob \| commitdiff \| raw \| diff to current
2014-09-02	Clifford Wolf	Create a default selection stack in RTLIL::Design:...	blob \| commitdiff \| raw \| diff to current
2014-09-01	Clifford Wolf	Using std::vector<RTLIL::State> instead of RTLIL::Const...	blob \| commitdiff \| raw \| diff to current
2014-08-31	Clifford Wolf	Added $lut support in test_cell, techmap, satgen	blob \| commitdiff \| raw \| diff to current
2014-08-30	Clifford Wolf	Added design->scratchpad	blob \| commitdiff \| raw \| diff to current
2014-08-30	Clifford Wolf	Added $alu cell type	blob \| commitdiff \| raw \| diff to current
2014-08-30	Clifford Wolf	Fixed module->addPmux()	blob \| commitdiff \| raw \| diff to current
2014-08-24	Clifford Wolf	Added is_signed argument to SigSpec.as_int() and Const...	blob \| commitdiff \| raw \| diff to current
2014-08-23	Clifford Wolf	Changed backend-api from FILE to std::ostream	blob \| commitdiff \| raw \| diff to current
2014-08-22	Clifford Wolf	Added emscripten (emcc) support to build system and...	blob \| commitdiff \| raw \| diff to current
2014-08-21	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2014-08-19	Clifford Wolf	Added mod->addGate() methods for new gate types	blob \| commitdiff \| raw \| diff to current
2014-08-17	Clifford Wolf	Improved sig.remove2() performance	blob \| commitdiff \| raw \| diff to current
2014-08-16	Clifford Wolf	Added module->uniquify()	blob \| commitdiff \| raw \| diff to current
2014-08-16	Clifford Wolf	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...	blob \| commitdiff \| raw \| diff to current
2014-08-15	Clifford Wolf	Renamed $lut ports to follow A-Y naming scheme	blob \| commitdiff \| raw \| diff to current
2014-08-15	Clifford Wolf	Renamed $_INV_ cell type to $_NOT_	blob \| commitdiff \| raw \| diff to current
2014-08-14	Clifford Wolf	Added RTLIL::SigSpec::to_sigbit_map()	blob \| commitdiff \| raw \| diff to current
2014-08-14	Clifford Wolf	Added sig.{replace,remove,extract} variants for std...	blob \| commitdiff \| raw \| diff to current
2014-08-14	Clifford Wolf	Added module->ports	blob \| commitdiff \| raw \| diff to current
2014-08-14	Clifford Wolf	Refactoring of CellType class	blob \| commitdiff \| raw \| diff to current
2014-08-14	Clifford Wolf	RIP $safe_pmux	blob \| commitdiff \| raw \| diff to current
2014-08-05	Clifford Wolf	Added support for truncating of wires to wreduce pass	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	Bugfix in "techmap -extern"	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	Removed at() method from RTLIL::IdString	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	No implicit conversion from IdString to anything else	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	Improvements in new RTLIL::IdString implementation	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	Implemented new reference counting RTLIL::IdString	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	More cleanups related to RTLIL::IdString usage	blob \| commitdiff \| raw \| diff to current
2014-08-01	Clifford Wolf	Added ModIndex helper class, some changes to RTLIL...	blob \| commitdiff \| raw \| diff to current
2014-08-01	Clifford Wolf	Packed SigBit::data and SigBit::offset in a union	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Renamed port access function on RTLIL::Cell, added...	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Added RTLIL::Monitor	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Added module->design and cell->module, wire->module...	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Moved some stuff to kernel/yosys.{h,cc}, using Yosys...	blob \| commitdiff \| raw \| diff to current
2014-07-29	Clifford Wolf	Added "techmap -map %{design-name}"	blob \| commitdiff \| raw \| diff to current
2014-07-29	Clifford Wolf	Added $shift and $shiftx cell types (needed for correct...	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Added wire->upto flag for signals such as "wire [0...	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Using log_assert() instead of assert()	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Added std::initializer_list<> constructor to SigSpec	blob \| commitdiff \| raw \| diff to current
2014-07-28	Clifford Wolf	Added cover() to all SigSpec constructors	blob \| commitdiff \| raw \| diff to current
2014-07-27	Clifford Wolf	Added proper Design->addModule interface	blob \| commitdiff \| raw \| diff to current
2014-07-27	Clifford Wolf	Added RTLIL::SigSpec::remove_const() handling of packed...	blob \| commitdiff \| raw \| diff to current
2014-07-27	Clifford Wolf	Added RTLIL::Module::wire(id) and cell(id) lookup functions	blob \| commitdiff \| raw \| diff to current
2014-07-27	Clifford Wolf	Refactoring: Renamed RTLIL::Design::modules to modules_	blob \| commitdiff \| raw \| diff to current
2014-07-27	Clifford Wolf	Added RTLIL::ObjIterator and RTLIL::ObjRange	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::cells to cells_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::wires to wires_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed more code to the new RTLIL::Wire constructors	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed a lot of code to the new RTLIL::Wire constructors	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Added RTLIL::Cell::has(portname)	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Merge automatic and manual code changes for new cell...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Manual fixes for new cell connections API	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed users of cell->connections_ to the new API...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Added some missing "const" in rtlil.h	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Added RTLIL::Module::connections()	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Added RTLIL::Module::connect(const RTLIL::SigSig&)	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Automatically pack SigSpec on copy/assign	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Added new RTLIL::Cell port access methods	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Renamed RTLIL::{Module,Cell}::connections to connections_	blob \| commitdiff \| raw \| diff to current
2014-07-25	Clifford Wolf	Added copy-constructor-like module->addCell(name, other...	blob \| commitdiff \| raw \| diff to current
2014-07-25	Clifford Wolf	Use only module->addCell() and module->remove() to...	blob \| commitdiff \| raw \| diff to current
2014-07-25	Clifford Wolf	Added RTLIL::SigSpec is_chunk()/as_chunk() API	blob \| commitdiff \| raw \| diff to current
2014-07-25	Clifford Wolf	Fixed typo in cover id	blob \| commitdiff \| raw \| diff to current
2014-07-24	Clifford Wolf	Replaced more old SigChunk programming patterns	blob \| commitdiff \| raw \| diff to current
2014-07-24	Clifford Wolf	Some improvements in SigSpec packing/unpacking and...	blob \| commitdiff \| raw \| diff to current
2014-07-24	Clifford Wolf	Small changes regarding cover() and check() in SigSpec	blob \| commitdiff \| raw \| diff to current
2014-07-24	Clifford Wolf	Added support for YOSYS_COVER_FILE env variable	blob \| commitdiff \| raw \| diff to current
2014-07-24	Clifford Wolf	Added cover() calls to RTLIL::SigSpec methods	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Added hashing to RTLIL::SigSpec relational and equal...	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Disabled RTLIL::SigSpec::check() in release builds	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Fixed release build	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Added RTLIL::SigSpec::repeat()	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Removed RTLIL::SigSpec::optimize()	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Turned RTLIL::SigSpec::optimize() to a no-op: a packed...	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Removed RTLIL::SigSpec::expand() method	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Replaced RTLIL::SigSpec::operator!=() with inline version	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Merge branch: Refactoring {SigSpec\|SigChunk}(RTLIL...	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ...	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ...	blob \| commitdiff \| raw \| diff to current
2014-07-23	Clifford Wolf	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ...	blob \| commitdiff \| raw \| diff to current
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