| 2019-04-18 |
Eddie Hung | Merge remote-tracking branch 'origin/clifford/whitebox... |
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| 2019-04-18 |
Clifford Wolf | Add "whitebox" attribute, add "read_verilog -wb" |
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| 2019-04-17 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig |
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| 2019-04-16 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig |
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| 2019-04-16 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig |
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| 2019-04-12 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig |
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| 2019-04-12 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig |
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| 2019-04-08 |
Eddie Hung | Merge branch 'master' into xaig |
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| 2019-04-05 |
Clifford Wolf | Add "read_ilang -lib" |
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| 2019-03-23 |
Clifford Wolf | Merge pull request #893 from YosysHQ/clifford/btormeminit |
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| 2019-03-23 |
Clifford Wolf | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend... |
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| 2019-03-19 |
Eddie Hung | Merge https://github.com/YosysHQ/yosys into read_aiger |
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| 2019-03-14 |
Clifford Wolf | Merge pull request #869 from cr1901/win-shell |
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| 2019-03-13 |
Clifford Wolf | Merge pull request #868 from YosysHQ/clifford/fixmem |
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| 2019-03-12 |
Clifford Wolf | Merge pull request #866 from YosysHQ/clifford/idstuff |
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| 2019-03-11 |
Clifford Wolf | Improve determinism of IdString DB for similar scripts |
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| 2019-02-26 |
Eddie Hung | Merge remote-tracking branch 'origin/master' into xaig |
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| 2019-02-26 |
Eddie Hung | Add IdString::ends_with() |
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| 2019-01-02 |
Clifford Wolf | Merge pull request #755 from Icenowy/anlogic-dram-init |
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| 2019-01-02 |
Clifford Wolf | Merge pull request #750 from Icenowy/anlogic-ff-init |
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| 2018-12-31 |
Clifford Wolf | Merge pull request #766 from Icenowy/anlogic-latches |
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| 2018-12-23 |
Clifford Wolf | Merge pull request #761 from whitequark/proc_clean_partial |
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| 2018-12-23 |
whitequark | proc_clean: remove any empty cases if all cases use... |
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| 2018-10-21 |
rafaeltp | cleaning up for PR |
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| 2018-10-21 |
rafaeltp | solves #675 |
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| 2018-10-19 |
Clifford Wolf | Merge pull request #672 from daveshah1/fix_bram |
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| 2018-10-18 |
Clifford Wolf | Merge pull request #659 from rubund/sv_interfaces |
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| 2018-10-12 |
Ruben Undheim | Support for 'modports' for System Verilog interfaces |
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| 2018-10-12 |
Ruben Undheim | Synthesis support for SystemVerilog interfaces |
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| 2018-09-17 |
Udi Finkelstein | Merge branch 'master' into pr_reg_wire_error |
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| 2018-08-22 |
Jim Lawson | Merge pull request #1 from YosysHQ/master |
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| 2018-08-18 |
Aman Goel | Merge pull request #3 from YosysHQ/master |
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| 2018-08-15 |
Clifford Wolf | Merge pull request #573 from cr1901/msys-64 |
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| 2018-08-15 |
Clifford Wolf | Merge pull request #591 from hzeller/virtual-override |
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| 2018-07-21 |
Henner Zeller | Consistent use of 'override' for virtual methods in... |
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| 2018-02-23 |
Clifford Wolf | Merge branch 'forall' |
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| 2018-02-23 |
Clifford Wolf | Add $allconst and $allseq cell types |
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| 2018-01-05 |
Clifford Wolf | Merge pull request #479 from Fatsie/latch_without_data |
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| 2018-01-05 |
Clifford Wolf | Bugfix in hierarchy handling of blackbox module ports |
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| 2017-12-14 |
Clifford Wolf | Merge branch 'master' into btor-ng |
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| 2017-12-14 |
Clifford Wolf | Add RTLIL::Const::is_fully_ones() |
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| 2017-12-14 |
Clifford Wolf | Add SigSpec::is_fully_ones() |
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| 2017-12-12 |
Clifford Wolf | Add SigSpec::is_fully_ones() |
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| 2017-09-09 |
Clifford Wolf | Add src arguments to all cell creator helper functions |
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| 2017-09-01 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2017-09-01 |
Clifford Wolf | Merge branch 'ChipScan-master' |
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| 2017-08-31 |
Andrew Zonenberg | Merge branch 'counter-extraction' of github.com:azonenb... |
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| 2017-08-30 |
Andrew Zonenberg | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2017-08-30 |
Jason Lowdermilk | Merge remote-tracking branch 'upstream/master' |
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| 2017-08-30 |
Clifford Wolf | Merge pull request #397 from azonenberg/gpak-libfixes |
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| 2017-08-30 |
Clifford Wolf | Add {get,set}_src_attribute() methods on RTLIL::AttrObject |
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| 2017-08-29 |
Jason Lowdermilk | Add support for source line tracking through synthesis... |
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| 2017-08-18 |
Clifford Wolf | Merge branch 'sim' |
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| 2017-08-18 |
Clifford Wolf | Add Const methods is_fully_zero(), is_fully_def(),... |
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| 2017-05-28 |
Clifford Wolf | Add "setundef -anyseq" |
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| 2017-05-17 |
Clifford Wolf | Add missing AndnotGate() and OrnotGate() declarations... |
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| 2017-05-17 |
Clifford Wolf | Add $_ANDNOT_ and $_ORNOT_ gates |
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| 2017-02-25 |
Clifford Wolf | Merge branch 'master' of https://github.com/klammerj... |
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| 2017-02-25 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2017-02-25 |
Clifford Wolf | Add $live and $fair cell types, add support for s_event... |
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| 2017-02-11 |
Clifford Wolf | Merge branch 'master' of https://github.com/stv0g/yosys... |
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| 2017-02-09 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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| 2017-02-04 |
Clifford Wolf | Add $cover cell type and SVA cover() support |
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| 2016-11-15 |
Clifford Wolf | Remember global declarations and defines accross read_v... |
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| 2016-10-14 |
Clifford Wolf | Added $anyseq cell type |
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| 2016-10-14 |
Clifford Wolf | Added $global_clock verilog syntax support for creating... |
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| 2016-10-11 |
Clifford Wolf | Added $ff and $_FF_ cell types |
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| 2016-09-07 |
Clifford Wolf | Improvements in assertpmux |
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| 2016-08-28 |
Clifford Wolf | Removed $predict again |
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| 2016-07-13 |
Clifford Wolf | Added basic support for $expect cells |
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| 2016-07-08 |
Clifford Wolf | Merge branch 'yosys-0.5-vtr' of https://github.com... |
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| 2016-06-19 |
Clifford Wolf | Merge branch 'sv_packages' of https://github.com/rubund... |
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| 2016-06-18 |
Ruben Undheim | A few modifications after pull request comments |
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| 2016-06-18 |
Ruben Undheim | Added support for SystemVerilog packages with localpara... |
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| 2016-02-02 |
Clifford Wolf | Added addBufGate module method |
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| 2016-01-31 |
Clifford Wolf | Meaningless coding style change |
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| 2016-01-31 |
Clifford Wolf | Merge branch 'rtlil_remove2_speedup' of https://github... |
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| 2016-01-30 |
Rick Altherr | rtlil: duplicate remove2() for std::set<> |
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| 2016-01-30 |
Rick Altherr | rtlil: change IdString comparison operators to take... |
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| 2015-12-07 |
Clifford Wolf | Merge pull request #108 from cseed/master |
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| 2015-11-26 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2015-11-26 |
Clifford Wolf | Removed dangling ';' in rtlil.h |
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| 2015-10-24 |
Clifford Wolf | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit... |
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| 2015-09-18 |
Clifford Wolf | Cosmetic fix in Module::addLut() |
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| 2015-08-16 |
Clifford Wolf | Added $tribuf and $_TBUF_ cell types |
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| 2015-08-14 |
Clifford Wolf | Spell check (by Larry Doolittle) |
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| 2015-07-02 |
Clifford Wolf | Fixed trailing whitespaces |
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| 2015-06-29 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2015-06-29 |
Clifford Wolf | Added design->rename(module, new_name) |
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| 2015-06-17 |
Clifford Wolf | Added "rename -top new_name" |
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| 2015-04-29 |
Clifford Wolf | Added $eq/$neq -> $logic_not/$reduce_bool optimization |
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| 2015-04-24 |
Clifford Wolf | Improved attributes API and handling of "src" attributes |
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| 2015-04-06 |
Clifford Wolf | Added support for initialized brams |
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| 2015-04-04 |
Clifford Wolf | Added "dffinit", Support for initialized Xilinx DFF |
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| 2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2015-02-24 |
Clifford Wolf | Some cleanups in "clean" |
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| 2015-02-07 |
Clifford Wolf | Added SigSpec::has_const() |
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| 2015-02-07 |
Clifford Wolf | Added cell->known(), cell->input(portname), cell->outpu... |
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| 2015-01-31 |
Clifford Wolf | Added "equiv_make -blacklist <file> -encfile <file>" |
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| 2015-01-30 |
Clifford Wolf | Synced RTLIL::unescape_id() to log_id() behavior |
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