2014-12-27 |
Clifford Wolf | More hashtable finetuning |
blob | commitdiff | raw |
2014-12-26 |
Clifford Wolf | Replaced std::unordered_set (nodict) with Yosys::pool |
blob | commitdiff | raw | diff to current |
2014-12-26 |
Clifford Wolf | Replaced std::unordered_map as implementation for Yosys... |
blob | commitdiff | raw | diff to current |
2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
blob | commitdiff | raw | diff to current |
2014-12-24 |
Clifford Wolf | Renamed extend() to extend_xx(), changed most users... |
blob | commitdiff | raw | diff to current |
2014-12-21 |
Clifford Wolf | Added support for multiple clock domains to "abc" pass |
blob | commitdiff | raw | diff to current |
2014-12-17 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
blob | commitdiff | raw | diff to current |
2014-12-16 |
Clifford Wolf | Fixed build with gcc 4.6 |
blob | commitdiff | raw | diff to current |
2014-12-11 |
Clifford Wolf | Added IdString::destruct_guard hack |
blob | commitdiff | raw | diff to current |
2014-12-08 |
Clifford Wolf | Added bool constructors to SigBit and SigSpec |
blob | commitdiff | raw | diff to current |
2014-12-08 |
Clifford Wolf | Added module->addDffe() and module->addDffeGate() |
blob | commitdiff | raw | diff to current |
2014-11-07 |
Clifford Wolf | Improved TopoSort determinism |
blob | commitdiff | raw | diff to current |
2014-10-17 |
Clifford Wolf | Fixed a few VS warnings |
blob | commitdiff | raw | diff to current |
2014-10-14 |
Clifford Wolf | Merge branch 'win32' |
blob | commitdiff | raw | diff to current |
2014-10-14 |
William Speirs | Made iterators extend std::iterator and added == operator |
blob | commitdiff | raw | diff to current |
2014-09-29 |
Clifford Wolf | Added support for "keep" on modules |
blob | commitdiff | raw | diff to current |
2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
blob | commitdiff | raw | diff to current |
2014-09-19 |
Clifford Wolf | Initialize RTLIL::Const from std::vector<bool> |
blob | commitdiff | raw | diff to current |
2014-09-04 |
Clifford Wolf | Removed $bu0 cell type |
blob | commitdiff | raw | diff to current |
2014-09-01 |
Clifford Wolf | Using std::vector<RTLIL::State> instead of RTLIL::Const... |
blob | commitdiff | raw | diff to current |
2014-08-31 |
Clifford Wolf | Added RTLIL::Const::size() |
blob | commitdiff | raw | diff to current |
2014-08-31 |
Clifford Wolf | Typo fixes in cell->*Param() API |
blob | commitdiff | raw | diff to current |
2014-08-30 |
Clifford Wolf | Added design->scratchpad |
blob | commitdiff | raw | diff to current |
2014-08-24 |
Clifford Wolf | Added is_signed argument to SigSpec.as_int() and Const... |
blob | commitdiff | raw | diff to current |
2014-08-22 |
Clifford Wolf | Added emscripten (emcc) support to build system and... |
blob | commitdiff | raw | diff to current |
2014-08-21 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
blob | commitdiff | raw | diff to current |
2014-08-19 |
Clifford Wolf | Added mod->addGate() methods for new gate types |
blob | commitdiff | raw | diff to current |
2014-08-16 |
Clifford Wolf | Added module->uniquify() |
blob | commitdiff | raw | diff to current |
2014-08-15 |
Clifford Wolf | Renamed $_INV_ cell type to $_NOT_ |
blob | commitdiff | raw | diff to current |
2014-08-15 |
Clifford Wolf | More idstring sort_by_* helpers and fixed tpl ordering... |
blob | commitdiff | raw | diff to current |
2014-08-14 |
Clifford Wolf | Added RTLIL::SigSpec::to_sigbit_map() |
blob | commitdiff | raw | diff to current |
2014-08-14 |
Clifford Wolf | Added sig.{replace,remove,extract} variants for std... |
blob | commitdiff | raw | diff to current |
2014-08-14 |
Clifford Wolf | Added module->ports |
blob | commitdiff | raw | diff to current |
2014-08-14 |
Clifford Wolf | RIP $safe_pmux |
blob | commitdiff | raw | diff to current |
2014-08-12 |
Clifford Wolf | Fixed SigBit(RTLIL::Wire *wire) constructor |
blob | commitdiff | raw | diff to current |
2014-08-05 |
Clifford Wolf | Added support for truncating of wires to wreduce pass |
blob | commitdiff | raw | diff to current |
2014-08-04 |
Clifford Wolf | Added RTLIL::IdString::in(...) |
blob | commitdiff | raw | diff to current |
2014-08-02 |
Clifford Wolf | Removed at() method from RTLIL::IdString |
blob | commitdiff | raw | diff to current |
2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else |
blob | commitdiff | raw | diff to current |
2014-08-02 |
Clifford Wolf | More bugfixes related to new RTLIL::IdString |
blob | commitdiff | raw | diff to current |
2014-08-02 |
Clifford Wolf | Limit size of log_signal buffer to 100 elements |
blob | commitdiff | raw | diff to current |
2014-08-02 |
Clifford Wolf | Improvements in new RTLIL::IdString implementation |
blob | commitdiff | raw | diff to current |
2014-08-02 |
Clifford Wolf | Implemented new reference counting RTLIL::IdString |
blob | commitdiff | raw | diff to current |
2014-08-02 |
Clifford Wolf | Fixed memory corruption related to id2cstr() |
blob | commitdiff | raw | diff to current |
2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
blob | commitdiff | raw | diff to current |
2014-08-01 |
Clifford Wolf | Preparations for RTLIL::IdString redesign: cleanup... |
blob | commitdiff | raw | diff to current |
2014-08-01 |
Clifford Wolf | Added ModIndex helper class, some changes to RTLIL... |
blob | commitdiff | raw | diff to current |
2014-08-01 |
Clifford Wolf | Packed SigBit::data and SigBit::offset in a union |
blob | commitdiff | raw | diff to current |
2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
blob | commitdiff | raw | diff to current |
2014-07-31 |
Clifford Wolf | Added RTLIL::Monitor |
blob | commitdiff | raw | diff to current |
2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module... |
blob | commitdiff | raw | diff to current |
2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
blob | commitdiff | raw | diff to current |
2014-07-30 |
Clifford Wolf | Added techmap CONSTMAP feature |
blob | commitdiff | raw | diff to current |
2014-07-30 |
Clifford Wolf | Added "kernel/yosys.h" and "kernel/yosys.cc" |
blob | commitdiff | raw | diff to current |
2014-07-29 |
Clifford Wolf | Added "techmap -map %{design-name}" |
blob | commitdiff | raw | diff to current |
2014-07-29 |
Clifford Wolf | Added $shift and $shiftx cell types (needed for correct... |
blob | commitdiff | raw | diff to current |
2014-07-28 |
Clifford Wolf | Added wire->upto flag for signals such as "wire [0... |
blob | commitdiff | raw | diff to current |
2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
blob | commitdiff | raw | diff to current |
2014-07-28 |
Clifford Wolf | Added std::initializer_list<> constructor to SigSpec |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Added proper Design->addModule interface |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Added RTLIL::SigSpecConstIterator |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Added RTLIL::Module::wire(id) and cell(id) lookup functions |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Added RTLIL::Design::modules() |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Added conversion from ObjRange to std::vector and std... |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Added RTLIL::ObjIterator and RTLIL::ObjRange |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Using std::move() in SigSpec move constructor |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Added RTLIL::SigSpec move constructor and move assignme... |
blob | commitdiff | raw | diff to current |
2014-07-27 |
Clifford Wolf | Mostly cosmetic changes to rtlil.h |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Changed more code to the new RTLIL::Wire constructors |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Changed a lot of code to the new RTLIL::Wire constructors |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Added some missing "const" in rtlil.h |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Added RTLIL::Module::connections() |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Added RTLIL::Module::connect(const RTLIL::SigSig&) |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Automatically pack SigSpec on copy/assign |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Added new RTLIL::Cell port access methods |
blob | commitdiff | raw | diff to current |
2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
blob | commitdiff | raw | diff to current |
2014-07-25 |
Clifford Wolf | Added copy-constructor-like module->addCell(name, other... |
blob | commitdiff | raw | diff to current |
2014-07-25 |
Clifford Wolf | Use only module->addCell() and module->remove() to... |
blob | commitdiff | raw | diff to current |
2014-07-25 |
Clifford Wolf | Added RTLIL::SigSpec is_chunk()/as_chunk() API |
blob | commitdiff | raw | diff to current |
2014-07-24 |
Clifford Wolf | Replaced more old SigChunk programming patterns |
blob | commitdiff | raw | diff to current |
2014-07-24 |
Clifford Wolf | Small changes regarding cover() and check() in SigSpec |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Added hashing to RTLIL::SigSpec relational and equal... |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Added RTLIL::SigSpec::repeat() |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::optimize() |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::expand() method |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Fixed all users of SigSpec::chunks_rw() and removed it |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Replaced RTLIL::SigSpec::operator!=() with inline version |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL... |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
blob | commitdiff | raw | diff to current |
2014-07-23 |
Clifford Wolf | Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL... |
blob | commitdiff | raw | diff to current |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: Added RTLIL::SigSpecIterator |
blob | commitdiff | raw | diff to current |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: added RTLIL::SigSpec::operator[] |
blob | commitdiff | raw | diff to current |
2014-07-22 |
Clifford Wolf | Removed RTLIL::SigChunk::compare() |
blob | commitdiff | raw | diff to current |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: added RTLIL::SigSpec::bits() and... |
blob | commitdiff | raw | diff to current |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::chunks... |
blob | commitdiff | raw | diff to current |
next |