| 2016-11-15 |
Clifford Wolf | Remember global declarations and defines accross read_v... |
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| 2016-10-14 |
Clifford Wolf | Added $anyseq cell type |
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| 2016-10-14 |
Clifford Wolf | Added $global_clock verilog syntax support for creating... |
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| 2016-10-11 |
Clifford Wolf | Added $ff and $_FF_ cell types |
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| 2016-09-07 |
Clifford Wolf | Improvements in assertpmux |
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| 2016-08-28 |
Clifford Wolf | Removed $predict again |
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| 2016-07-13 |
Clifford Wolf | Added basic support for $expect cells |
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| 2016-07-08 |
Clifford Wolf | Merge branch 'yosys-0.5-vtr' of https://github.com... |
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| 2016-06-19 |
Clifford Wolf | Merge branch 'sv_packages' of https://github.com/rubund... |
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| 2016-06-18 |
Ruben Undheim | A few modifications after pull request comments |
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| 2016-06-18 |
Ruben Undheim | Added support for SystemVerilog packages with localpara... |
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| 2016-02-02 |
Clifford Wolf | Added addBufGate module method |
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| 2016-01-31 |
Clifford Wolf | Meaningless coding style change |
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| 2016-01-31 |
Clifford Wolf | Merge branch 'rtlil_remove2_speedup' of https://github... |
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| 2016-01-30 |
Rick Altherr | rtlil: duplicate remove2() for std::set<> |
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| 2016-01-30 |
Rick Altherr | rtlil: change IdString comparison operators to take... |
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| 2015-12-07 |
Clifford Wolf | Merge pull request #108 from cseed/master |
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| 2015-11-26 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2015-11-26 |
Clifford Wolf | Removed dangling ';' in rtlil.h |
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| 2015-10-24 |
Clifford Wolf | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit... |
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| 2015-09-18 |
Clifford Wolf | Cosmetic fix in Module::addLut() |
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| 2015-08-16 |
Clifford Wolf | Added $tribuf and $_TBUF_ cell types |
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| 2015-08-14 |
Clifford Wolf | Spell check (by Larry Doolittle) |
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| 2015-07-02 |
Clifford Wolf | Fixed trailing whitespaces |
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| 2015-06-29 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2015-06-29 |
Clifford Wolf | Added design->rename(module, new_name) |
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| 2015-06-17 |
Clifford Wolf | Added "rename -top new_name" |
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| 2015-04-29 |
Clifford Wolf | Added $eq/$neq -> $logic_not/$reduce_bool optimization |
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| 2015-04-24 |
Clifford Wolf | Improved attributes API and handling of "src" attributes |
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| 2015-04-06 |
Clifford Wolf | Added support for initialized brams |
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| 2015-04-04 |
Clifford Wolf | Added "dffinit", Support for initialized Xilinx DFF |
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| 2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2015-02-24 |
Clifford Wolf | Some cleanups in "clean" |
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| 2015-02-07 |
Clifford Wolf | Added SigSpec::has_const() |
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| 2015-02-07 |
Clifford Wolf | Added cell->known(), cell->input(portname), cell->outpu... |
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| 2015-01-31 |
Clifford Wolf | Added "equiv_make -blacklist <file> -encfile <file>" |
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| 2015-01-30 |
Clifford Wolf | Synced RTLIL::unescape_id() to log_id() behavior |
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| 2015-01-23 |
Clifford Wolf | Added dict/pool.sort() |
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| 2015-01-19 |
Clifford Wolf | Added equiv_make command |
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| 2015-01-01 |
Clifford Wolf | Removed SigSpec::extend_xx() api |
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| 2014-12-31 |
Clifford Wolf | Progress in memory_bram |
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| 2014-12-31 |
Clifford Wolf | IdString optimization |
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| 2014-12-30 |
Clifford Wolf | added hashlib::mkhash_init |
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| 2014-12-29 |
Clifford Wolf | Added "yosys -X" |
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| 2014-12-29 |
Clifford Wolf | Converting "share" to dict<> and pool<> complete |
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| 2014-12-28 |
Clifford Wolf | Added mkhash_xorshift() |
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| 2014-12-28 |
Clifford Wolf | Fixed performance bug in object hashing |
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| 2014-12-28 |
Clifford Wolf | Renamed hashmap.h to hashlib.h, some related improvements |
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| 2014-12-27 |
Clifford Wolf | More dict/pool related changes |
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| 2014-12-27 |
Clifford Wolf | More hashtable finetuning |
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| 2014-12-26 |
Clifford Wolf | Replaced std::unordered_set (nodict) with Yosys::pool |
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| 2014-12-26 |
Clifford Wolf | Replaced std::unordered_map as implementation for Yosys... |
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| 2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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| 2014-12-24 |
Clifford Wolf | Renamed extend() to extend_xx(), changed most users... |
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| 2014-12-21 |
Clifford Wolf | Added support for multiple clock domains to "abc" pass |
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| 2014-12-17 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2014-12-16 |
Clifford Wolf | Fixed build with gcc 4.6 |
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| 2014-12-11 |
Clifford Wolf | Added IdString::destruct_guard hack |
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| 2014-12-08 |
Clifford Wolf | Added bool constructors to SigBit and SigSpec |
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| 2014-12-08 |
Clifford Wolf | Added module->addDffe() and module->addDffeGate() |
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| 2014-11-07 |
Clifford Wolf | Improved TopoSort determinism |
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| 2014-10-17 |
Clifford Wolf | Fixed a few VS warnings |
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| 2014-10-14 |
Clifford Wolf | Merge branch 'win32' |
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| 2014-10-14 |
William Speirs | Made iterators extend std::iterator and added == operator |
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| 2014-09-29 |
Clifford Wolf | Added support for "keep" on modules |
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| 2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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| 2014-09-19 |
Clifford Wolf | Initialize RTLIL::Const from std::vector<bool> |
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| 2014-09-04 |
Clifford Wolf | Removed $bu0 cell type |
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| 2014-09-01 |
Clifford Wolf | Using std::vector<RTLIL::State> instead of RTLIL::Const... |
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| 2014-08-31 |
Clifford Wolf | Added RTLIL::Const::size() |
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| 2014-08-31 |
Clifford Wolf | Typo fixes in cell->*Param() API |
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| 2014-08-30 |
Clifford Wolf | Added design->scratchpad |
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| 2014-08-24 |
Clifford Wolf | Added is_signed argument to SigSpec.as_int() and Const... |
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| 2014-08-22 |
Clifford Wolf | Added emscripten (emcc) support to build system and... |
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| 2014-08-21 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2014-08-19 |
Clifford Wolf | Added mod->addGate() methods for new gate types |
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| 2014-08-16 |
Clifford Wolf | Added module->uniquify() |
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| 2014-08-15 |
Clifford Wolf | Renamed $_INV_ cell type to $_NOT_ |
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| 2014-08-15 |
Clifford Wolf | More idstring sort_by_* helpers and fixed tpl ordering... |
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| 2014-08-14 |
Clifford Wolf | Added RTLIL::SigSpec::to_sigbit_map() |
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| 2014-08-14 |
Clifford Wolf | Added sig.{replace,remove,extract} variants for std... |
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| 2014-08-14 |
Clifford Wolf | Added module->ports |
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| 2014-08-14 |
Clifford Wolf | RIP $safe_pmux |
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| 2014-08-12 |
Clifford Wolf | Fixed SigBit(RTLIL::Wire *wire) constructor |
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| 2014-08-05 |
Clifford Wolf | Added support for truncating of wires to wreduce pass |
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| 2014-08-04 |
Clifford Wolf | Added RTLIL::IdString::in(...) |
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| 2014-08-02 |
Clifford Wolf | Removed at() method from RTLIL::IdString |
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| 2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else |
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| 2014-08-02 |
Clifford Wolf | More bugfixes related to new RTLIL::IdString |
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| 2014-08-02 |
Clifford Wolf | Limit size of log_signal buffer to 100 elements |
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| 2014-08-02 |
Clifford Wolf | Improvements in new RTLIL::IdString implementation |
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| 2014-08-02 |
Clifford Wolf | Implemented new reference counting RTLIL::IdString |
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| 2014-08-02 |
Clifford Wolf | Fixed memory corruption related to id2cstr() |
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| 2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
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| 2014-08-01 |
Clifford Wolf | Preparations for RTLIL::IdString redesign: cleanup... |
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| 2014-08-01 |
Clifford Wolf | Added ModIndex helper class, some changes to RTLIL... |
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| 2014-08-01 |
Clifford Wolf | Packed SigBit::data and SigBit::offset in a union |
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| 2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
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| 2014-07-31 |
Clifford Wolf | Added RTLIL::Monitor |
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| 2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module... |
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