memory_bram: Fix initdata bit order after shuffling
[yosys.git] / kernel /
2017-05-17 Clifford WolfAdd missing AndnotGate() and OrnotGate() declarations...
2017-05-17 Clifford WolfAdd $_ANDNOT_ and $_ORNOT_ gates
2017-04-05 Clifford WolfAdd ConstEval defaultval feature
2017-03-28 Clifford WolfAdd front-end detection for *.tcl files
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-23 Clifford WolfFix mingw compile issue (2nd attempt)
2017-02-23 Clifford WolfFix mingw compile issue (maybe.. I can't test it)
2017-02-16 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-16 Clifford WolfFix eval implementation of $_NOR_
2017-02-14 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-12 Clifford WolfAdd "yosys -w" for suppressing warnings
2017-02-11 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-11 Clifford WolfAdd log_wire() API
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-05 Clifford WolfFix undef propagation bug in $pmux SAT model
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2017-01-31 Clifford WolfMerge branch 'opt_compare_pr' of https://github.com...
2017-01-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-01-25 Clifford WolfFix RTLIL::Memory::start_offset initialization
2017-01-01 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-31 Clifford WolfBugfix in RTLIL::SigSpec::remove2()
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-23 Clifford WolfSimplified log_spacer() code
2016-12-22 Clifford WolfAdded "yosys -W regex"
2016-12-21 Clifford WolfAdded AIGER back-end to automatic back-end detection
2016-12-17 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-13 Clifford WolfBugfix in comment handling
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v...
2016-10-14 Clifford WolfSome minor build fixes for Visual C
2016-10-14 Clifford WolfAdded $anyseq cell type
2016-10-14 Clifford WolfAdded $global_clock verilog syntax support for creating...
2016-10-11 Clifford WolfAdded $ff and $_FF_ cell types
2016-10-11 Clifford Wolfdefine PATH_MAX if not defined by limits.h
2016-09-07 Clifford WolfImprovements in assertpmux
2016-08-30 Clifford WolfRemoved $aconst cell type
2016-08-28 Clifford WolfRemoved $predict again
2016-08-27 Clifford WolfFixed handling of transparent bram rd ports on ROMs
2016-08-22 Clifford WolfAdded glob support to all front-ends
2016-08-16 Clifford WolfMerge pull request #203 from cr1901/master
2016-08-16 William D. JonesAdd MSYS2-compatible build.
2016-08-16 Clifford WolfUse _Exit(0) on win32, always use _Exit(1) in log_error()
2016-08-09 Clifford WolfAdded log_const() API
2016-08-08 Yury GribovUse /proc/self/exe on Cygwin as well.
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-27 Clifford WolfAdded SatGen support for $anyconst
2016-07-27 Clifford WolfRemoved $predict support from SatGen
2016-07-27 Clifford WolfAdded $anyconst and $aconst
2016-07-27 Clifford WolfAdded "read_verilog -dump_rtlil"
2016-07-25 Clifford WolfRenamed AbstractCellEdgesDatabase::add_cell() to add_ed...
2016-07-24 Clifford WolfImprovements in CellEdgesDatabase
2016-07-24 Clifford WolfAdded CellEdgesDatabase API
2016-07-22 Clifford WolfAdded satgen initstate support
2016-07-21 Clifford WolfAdded $initstate cell type and vlog function
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund...
2016-06-18 Ruben UndheimA few modifications after pull request comments
2016-06-18 Ruben UndheimAdded support for SystemVerilog packages with localpara...
2016-06-17 Clifford WolfAdded $sop SAT model
2016-06-17 Clifford WolfImproved support for $sop cells
2016-06-17 Clifford WolfAdded $sop cell type and "abc -sop"
2016-05-14 Clifford WolfAdded missing "#define HASHLIB_H"
2016-05-08 Clifford WolfInclude <cmath> in yosys.h
2016-05-07 Clifford WolfFixes for MXE build
2016-04-25 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-24 Clifford WolfAdded "yosys -D ALL"
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-04-16 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-16 Clifford WolfMinor hashlib bugfix
2016-04-07 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-05 Clifford WolfHashlib indenting fix
2016-04-01 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-03-31 Clifford WolfAdded ScriptPass helper class for script-like passes
2016-03-31 Clifford WolfAdded log_dump() support for dict<> and pool<> containers
2016-03-31 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-03-30 Clifford WolfWe have 2016 for a while now
2016-03-30 Clifford WolfAdded .vhd file extension support
2016-03-28 Clifford WolfMerge pull request #137 from ravenexp/master
2016-03-28 Clifford WolfMerge pull request #138 from SebKuzminsky/help-typo
2016-03-26 Sebastian Kuzminskyfix a cut-n-paste error in the -h help
2016-03-26 Sergey KvachonokEmbed DATDIR make variable value into yosys binary.
2016-02-15 Clifford WolfUse easyer-to-read unoptimized ceil_log2()
2016-02-14 Clifford WolfFixed more visual studio warnings
2016-02-13 Clifford WolfFixed some visual studio warnings
2016-02-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-02-13 Clifford WolfAdded "int ceil_log2(int)" function
2016-02-02 Clifford WolfAdded addBufGate module method
2016-02-01 Clifford WolfSigMap performance improvement
2016-02-01 Clifford Wolfhashlib mfp<> performance improvements
2016-01-31 Clifford WolfAdded reserve() method to haslib classes and
2016-01-31 Clifford WolfMerge branch 'rtlil_remove2_speedup' of https://github...
2016-01-31 Rick Altherrrtlil: Improve performance of SigSpec::extract(SigSpec...
2016-01-31 Rick Altherrrtlil: speed up SigSpec::sort_and_unify()
next