Various improvements regarding logic loops in "share" results
[yosys.git] / kernel /
2014-09-21 Clifford WolfAssert on new logic loops in "share" pass
2014-09-19 Clifford WolfInitialize RTLIL::Const from std::vector<bool>
2014-09-16 Clifford WolfAdded new CodingReadme file (replaces CodingStyle and...
2014-09-15 Clifford WolfAdded the obvious optimizations to alumacc $macc generator
2014-09-14 Clifford WolfFixed monitor notifications for removed cell
2014-09-14 Clifford WolfAdded "synth" command
2014-09-08 Clifford WolfSimplified $fa undef model
2014-09-08 Clifford WolfAdded $lcu cell type
2014-09-08 Clifford WolfAdded "$fa" cell type
2014-09-06 Clifford WolfAdded $macc eval model
2014-09-06 Clifford WolfAdded $macc SAT model
2014-09-06 Clifford WolfAdded $macc cell type
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-09-04 Clifford WolfRemoved $bu0 cell type
2014-09-03 Clifford WolfUsing $pos models for $bu0
2014-09-03 Clifford WolfFixes in $alu SAT- and eval-models
2014-09-02 Clifford WolfCreate a default selection stack in RTLIL::Design:...
2014-09-02 Clifford WolfSmall bug fixes in $not, $neg, and $shiftx models
2014-09-01 Clifford WolfAdded ConstEval model for $alu cells
2014-09-01 Clifford WolfAdded SAT model for $alu cells
2014-09-01 Clifford WolfUsing std::vector<RTLIL::State> instead of RTLIL::Const...
2014-08-31 Clifford WolfFixed return size of const_*() eval functions
2014-08-31 Clifford WolfAdded RTLIL::Const::size()
2014-08-31 Clifford WolfAdded eval model for $lut cells
2014-08-31 Clifford WolfTypo fixes in cell->*Param() API
2014-08-31 Clifford WolfAdded $lut support in test_cell, techmap, satgen
2014-08-30 Clifford WolfAdded design->scratchpad
2014-08-30 Clifford WolfAdded $alu cell type
2014-08-30 Clifford WolfFixed module->addPmux()
2014-08-24 Clifford WolfAdded is_signed argument to SigSpec.as_int() and Const...
2014-08-23 Clifford WolfRemoved compatbility.{h,cc}: Not using open_memstream...
2014-08-23 Clifford WolfChanged frontend-api from FILE to std::istream
2014-08-23 Clifford WolfChanged backend-api from FILE to std::ostream
2014-08-22 Clifford WolfAdded emscripten (emcc) support to build system and...
2014-08-22 Clifford WolfAdded "plugin" command
2014-08-21 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-08-19 Clifford WolfAdded mod->addGate() methods for new gate types
2014-08-17 Clifford WolfFixed proc_{self,share}_dirname error handling
2014-08-17 Clifford WolfImproved sig.remove2() performance
2014-08-16 Clifford WolfAdded stackmap<> container
2014-08-16 Clifford WolfRenamed toposort.h to utils.h
2014-08-16 Clifford WolfAdded module->uniquify()
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_...
2014-08-16 Clifford WolfAdded CellTypes::cell_evaluable()
2014-08-16 Clifford WolfAdded log_spacer()
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-15 Clifford WolfMore idstring sort_by_* helpers and fixed tpl ordering...
2014-08-15 Clifford WolfAdded Frontend "+/" filename syntax for files from...
2014-08-14 Clifford WolfAdded RTLIL::SigSpec::to_sigbit_map()
2014-08-14 Clifford WolfAdded sig.{replace,remove,extract} variants for std...
2014-08-14 Clifford WolfAdded module->ports
2014-08-14 Clifford WolfRefactoring of CellType class
2014-08-14 Clifford WolfRIP $safe_pmux
2014-08-12 Clifford WolfFixed SigBit(RTLIL::Wire *wire) constructor
2014-08-11 Clifford WolfAnother build fix by americanrouter (via reddit)
2014-08-07 Clifford WolfFixed build with gcc-4.6
2014-08-05 Clifford WolfAdded support for truncating of wires to wreduce pass
2014-08-04 Clifford WolfAdded RTLIL::IdString::in(...)
2014-08-03 Clifford WolfAdded query() API to ModIndex
2014-08-03 Clifford WolfAdded ID() macro for static IdStrings
2014-08-02 Clifford WolfFixed a va_list corruption in logv_error()
2014-08-02 Clifford WolfBugfix in "techmap -extern"
2014-08-02 Clifford WolfRemoved at() method from RTLIL::IdString
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-08-02 Clifford WolfMore bugfixes related to new RTLIL::IdString
2014-08-02 Clifford WolfLimit size of log_signal buffer to 100 elements
2014-08-02 Clifford WolfImprovements in new RTLIL::IdString implementation
2014-08-02 Clifford WolfImplemented new reference counting RTLIL::IdString
2014-08-02 Clifford WolfFixed memory corruption related to id2cstr()
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-08-01 Clifford WolfPreparations for RTLIL::IdString redesign: cleanup...
2014-08-01 Clifford WolfAdded logfile hash to statistics footer
2014-08-01 Clifford WolfAdded per-pass cpu usage statistics
2014-08-01 Clifford WolfAdded ModIndex helper class, some changes to RTLIL...
2014-08-01 Clifford WolfPacked SigBit::data and SigBit::offset in a union
2014-07-31 Clifford WolfRenamed modwalker.h to modtools.h
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfAdded "trace" command
2014-07-31 Clifford WolfAdded RTLIL::Monitor
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-30 Clifford WolfAdded "yosys -A"
2014-07-30 Clifford WolfAdded "yosys -Q"
2014-07-30 Clifford WolfAdded techmap CONSTMAP feature
2014-07-30 Clifford WolfAdded write_file command
2014-07-30 Clifford WolfUsing native ezSAT shift ops in satgen, fixed $shift...
2014-07-30 Clifford WolfAdded "log_dump_val_worker(char *v)"
2014-07-30 Clifford WolfAdded "kernel/yosys.h" and "kernel/yosys.cc"
2014-07-29 Clifford WolfAdded "test_cell" command
2014-07-29 Clifford WolfRenamed "write_autotest" to "test_autotb" and moved...
2014-07-29 Clifford WolfAdded "techmap -map %{design-name}"
2014-07-29 Clifford WolfAdded $shift and $shiftx cell types (needed for correct...
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-28 Clifford WolfAdded std::initializer_list<> constructor to SigSpec
2014-07-28 Clifford WolfAdded cover() to all SigSpec constructors
2014-07-27 Clifford WolfAdded proper Design->addModule interface
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