Removed RTLIL::SigSpec::optimize()
[yosys.git] / kernel /
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::optimize()
2014-07-23 Clifford WolfTurned RTLIL::SigSpec::optimize() to a no-op: a packed...
2014-07-23 Clifford WolfRemoved RTLIL::SigSpec::expand() method
2014-07-23 Clifford WolfFixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 Clifford WolfReplaced RTLIL::SigSpec::operator!=() with inline version
2014-07-23 Clifford WolfMerge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfRefactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
2014-07-23 Clifford WolfSome cleanups in RTLIL::SigChunk::SigChunk(const RTLIL...
2014-07-22 Clifford WolfSigSpec refactoring: More cleanups of old SigSpec use...
2014-07-22 Clifford WolfSigSpec refactoring: Added RTLIL::SigSpecIterator
2014-07-22 Clifford WolfSigSpec refactoring: added RTLIL::SigSpec::operator[]
2014-07-22 Clifford WolfSigSpec refactoring: rewrote some RTLIL::SigSpec method...
2014-07-22 Clifford WolfRemoved RTLIL::SigChunk::compare()
2014-07-22 Clifford WolfSigSpec refactoring: added RTLIL::SigSpec::bits() and...
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::size()...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed the SigSpec members to...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-21 Clifford WolfAdded support for scripts with labels
2014-07-21 Clifford WolfReplaced depricated NEW_WIRE macro with module->addWire...
2014-07-21 Clifford WolfRemoved deprecated module->new_wire()
2014-07-21 Clifford WolfBugfix in satgen for cells with wider in- than outputs.
2014-07-21 Clifford WolfAdded module->remove(), module->addWire(), module-...
2014-07-21 Clifford WolfAdded log_ping()
2014-07-20 Clifford WolfAdded call_on_selection() and call_on_module() API
2014-07-20 Clifford WolfAdded std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
2014-07-20 Clifford WolfAdded SIZE() macro
2014-07-20 Clifford WolfAdded log_cell()
2014-07-19 Clifford WolfFixed log_id() memory corruption
2014-07-19 Clifford WolfAdded ModWalker helper class
2014-07-19 Clifford WolfSome "const" cleanups in SigMap
2014-07-18 Clifford WolfAdded automatic conversion from RTLIL::SigSpec to std...
2014-07-18 Clifford WolfAdded function-like cell creation helpers
2014-07-18 Clifford WolfAdded log_id() helper function
2014-07-17 Clifford WolfFixed RTLIL::SigSpec::append_bit() for appending constants
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
2014-07-16 Clifford WolfChanged the $mem/$memwr WR_EN input to a per-data-bit...
2014-07-11 Clifford WolfUse "verilog -sv" to parse .sv files
2014-06-07 Clifford WolfAdd support for cell arrays
2014-06-04 Clifford WolfImproved error message for options after front-end...
2014-05-03 Clifford Wolfworkaround for OpenBSD 'stdout' implementation
2014-05-02 Clifford Wolfworkaround for OpenBSD 'stdin' implementation
2014-03-31 Clifford WolfAdded support for dlatchsr cells
2014-03-17 Clifford WolfFixed typo in RTLIL::Module::addAdff()
2014-03-15 Clifford WolfFixed typo in RTLIL::Module::{addSshl,addSshr}
2014-03-15 Clifford WolfAdded RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate...
2014-03-14 Clifford WolfAdded log_dump() support for generic pointers
2014-03-14 Clifford WolfProgress in Verific bindings
2014-03-14 Clifford WolfAdded RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
2014-03-13 Clifford WolfHotfix for kernel/compatibility.h
2014-03-13 Clifford WolfMerge branch 'master' of https://github.com/Siesh1oo...
2014-03-13 Clifford WolfMerged OSX fixes from Siesh1oo with some modifications
2014-03-13 Siesh1oo - Makefile, kernel/posix_compatibility.h/.cc: replay...
2014-03-13 Siesh1ooMerge branch 'master' of https://github.com/Siesh1oo...
2014-03-12 Siesh1oo - kernel/register.h, kernel/driver.cc: refactor rewrit...
2014-03-12 Siesh1oo - kernel/register.h, kernel/driver.cc: refactor rewrit...
2014-03-12 Siesh1ooMerge branch 'master' of https://github.com/Siesh1oo...
2014-03-12 Clifford WolfAdded libs/minisat (copy of minisat git master)
2014-03-11 Siesh1ooRebase to cliffordwolf repo HEAD finished.
2014-03-11 Clifford WolfMerged a few fixes for non-posix systems from github...
2014-03-10 Siesh1oo - Makefile, kernel/posix_compatibility.h/.cc: provide...
2014-03-10 Siesh1oo - kernel/register.cc: need to #include <cerrno> or...
2014-03-10 Siesh1oo - kernel/driver.cc: need to #include <cerrno> or errno...
2014-03-10 Siesh1oo - kernel/log.h: add rusage()-based fallback for system...
2014-03-10 Clifford WolfFixed a typo in RTLIL::Module::addReduce...
2014-03-10 Clifford WolfAdded RTLIL::Module::add... helper methods
2014-03-06 Clifford WolfFixed use of frozen literals in SatGen
2014-03-06 Clifford WolfStrictly zero-extend unsigned A-inputs of shift operations
2014-02-27 Clifford WolfFixed const folding of $bu0 cells
2014-02-26 Clifford WolfAdded support for $bu0 to SatGen
2014-02-23 Clifford WolfAdded support for Minisat::SimpSolver + ezSAT frezze...
2014-02-23 Clifford WolfFixed small memory leak in Pass::call()
2014-02-20 Clifford WolfAdded "design -push" and "design -pop"
2014-02-08 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-08 Clifford WolfImproved checking of internal cell conventions
2014-02-07 Clifford WolfAdded $slice and $concat to CellTypes list
2014-02-07 Clifford WolfAdded $slice and $concat cell types
2014-02-07 Clifford WolfStronger checking of internal cells
2014-02-07 Clifford WolfAdded echo command
2014-02-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-06 Clifford WolfAdded generic RTLIL::SigSpec::parse_sel() with support...
2014-02-06 Clifford WolfAdded support for #-comments in same line as command
2014-02-06 Clifford WolfAdded support for backslash continuation in script...
2014-02-04 Clifford WolfFixed bug in sequential sat proofs and improved handlin...
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-02-02 Clifford WolfAdded RTLIL::SigSpec::to_single_sigbit()
2014-01-30 Clifford WolfAdded yosys -H for command list
2014-01-29 Clifford WolfAdded -h command line option
2014-01-24 Clifford WolfRestored IdString::check()
2014-01-24 Clifford WolfMerge branch 'btor' of https://github.com/ahmedirfan198...
2014-01-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-19 Clifford WolfAdded $assert support to satgen
2014-01-19 Clifford WolfAdded $assert cell
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-18 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
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