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Add Tercel PHY reset synchronization
[microwatt.git] / litedram / generated / sim / litedram_core.init
2020-08-13 Michael NeulingMerge pull request #235 from paulusmack/master commit | commitdiff
2020-08-07 Michael NeulingMerge pull request #229 from ozbenh/litedram commit | commitdiff
2020-07-08 Benjamin Herrenschmidtlitedram: Regenerate commit | commitdiff
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup commit | commitdiff
2020-06-29 Michael NeulingMerge pull request #213 from ozbenh/uart16550 commit | commitdiff
2020-06-29 Michael NeulingMerge pull request #212 from ozbenh/liteeth commit | commitdiff
2020-06-23 Benjamin Herrenschmidtconsole: Add support for the 16550 UART commit | commitdiff
2020-06-23 Benjamin Herrenschmidtliteeth: Hook up LiteX LiteEth ethernet controller commit | commitdiff
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster commit | commitdiff
2020-06-17 Paul MackerrasMerge pull request #207 from ozbenh/misc commit | commitdiff
2020-06-14 Benjamin Herrenschmidtsoc: Rename wb_dram_ctrl to wb_ext_io and rework decoding commit | commitdiff
2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi commit | commitdiff
2020-06-13 Benjamin Herrenschmidtspi: Add booting from flash to litedram init commit | commitdiff
2020-06-05 Paul MackerrasMerge pull request #191 from ozbenh/litedram commit | commitdiff
2020-06-05 Benjamin Herrenschmidtlitedram: Remove old "VexRiscV" based initializations commit | commitdiff
2020-06-05 Benjamin Herrenschmidtlitedram: Update to latest LiteX/LiteDRAM version commit | commitdiff
2020-06-05 Benjamin Herrenschmidtlitedram: Test bench commit | commitdiff
2020-06-05 Benjamin Herrenschmidtlitedram: Add an L2 cache with store queue commit | commitdiff
2020-06-05 Benjamin Herrenschmidtlitedram: Add support for booting without BRAM commit | commitdiff
2020-06-05 Benjamin Herrenschmidtlitedram: Add simulation support commit | commitdiff